project.name

Sreedhar

Member since: 8 months

Educational Institution: Not Entered

Country: Not Entered

multiplexer

multiplexer
Public
project.name

COMBINATIONAL CIRCUIT USING BASIC GATES

COMBINATIONAL CIRCUIT USING BASIC GATES
Public
project.name

COMBINATIONAL CIRCUIT USING NAND GATE

COMBINATIONAL CIRCUIT USING NAND GATE
Public
project.name

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS
Public
project.name

HALF ADDER USING EXOR GATE

HALF ADDER USING EXOR GATE
Public
project.name

HALF ADDER USING NAND GATE

HALF ADDER USING NAND GATE
Public
project.name

HALF SUBTRACTOR USING EXOR GATE

HALF SUBTRACTOR USING EXOR GATE
Public
project.name

HALF SUBTRACTOR USING BASIC GATES

HALF SUBTRACTOR USING BASIC GATES
Public
project.name

HALF SUBTRACTOR USING NAND GATE

HALF SUBTRACTOR USING NAND GATE
Public
project.name

FULL SUBTRACTOR USING BASIC GATES

FULL SUBTRACTOR USING BASIC GATES
Public
project.name

FULL SUBTRACTOR USING EXOR GATE

FULL SUBTRACTOR USING EXOR GATE
Public
project.name

FULL SUBTRACTOR USING NAND GATE ONLY

FULL SUBTRACTOR USING NAND GATE ONLY
Public
project.name

FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
Public
project.name

HALF ADDER USING BASIC GATES

HALF ADDER USING BASIC GATES
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

COMBINATIONAL LOGIC CIRCUIT LV2

COMBINATIONAL LOGIC CIRCUIT LV2
Public
project.name

Exp 1 level-02

Exp 1 level-02
Public
project.name

COMBINATIONAL LOGIC CIRCUIT LV1

COMBINATIONAL LOGIC CIRCUIT LV1
Public
project.name

half adder using NAND gate

half adder using NAND gate
Public
project.name

Full Adder using two Half Adder

Full Adder using two Half Adder
Public
project.name

FULL ADDER

FULL ADDER
Public
project.name

Multiplexer

Multiplexer
Public
project.name

S R LATCH USING ENABLE INPUT

S R LATCH USING ENABLE INPUT
Public
project.name

J K FLIP FLOP

J K FLIP FLOP
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

BASIC GATES RELIZATION OF 4:1 MUX

BASIC GATES RELIZATION OF 4:1 MUX
Public
project.name

LOGIC CIRCUIT OF 2-TO-1MULTIPLEXER

LOGIC CIRCUIT OF 2-TO-1MULTIPLEXER
Public
project.name

1:2 DMUX USING BASIC GATES

1:2 DMUX USING BASIC GATES
Public
project.name

4:2 ENCODER USING BASIC GATES

4:2 ENCODER USING BASIC GATES
Public
project.name

1:4 DMUX USING BASIC GATES

1:4 DMUX USING BASIC GATES
Public
project.name

2:4 DECODER USING BASIC GATES

2:4 DECODER USING BASIC GATES
Public
project.name

SR LATCH

SR LATCH
Public
project.name
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