project.name

Tejdeep

Member since: 9 months

Educational Institution: Not Entered

Country: Not Entered

EXPERIMENT1 L-2

EXPERIMENT1 L-2
Public
project.name

EXPERIMENT1 L-2

EXPERIMENT1 L-2
Public
project.name

EXPERIMENT2 L-1

EXPERIMENT2 L-1
Public
project.name

Untitled

Untitled
Public
project.name

experiment 2 level 1

experiment 2 level 1
Public
project.name

Combinational logic circuit using basic gates

Combinational logic circuit using basic gates
Public
project.name

2-1 Multiplexer

2-1 Multiplexer
Public
project.name

2-1 Multiplexer

2-1 Multiplexer
Public
project.name

Multiplexer

Multiplexer
Public
project.name

Experiment 4

Experiment 4
Public
project.name

EXPERIMENT1 L-1

EXPERIMENT1 L-1
Public
project.name

SR Flip Flop

SR Flip Flop
Public
project.name

Clocked SR Flip Flop

Clocked SR Flip Flop
Public
project.name

JK Flip flop

JK Flip flop
Public
project.name

Combinational logic circuit using basic gates

Combinational logic circuit using basic gates
Public
project.name

Comparator

Comparator
Public
project.name

4x1 Multiplexer

4x1 Multiplexer
Public
project.name
No result image
Tejdeep doesn't have any favourites.
No result image
Tejdeep is not a collaborator of any project.