project.name

Raj Prasad Singha

Member since: 1 year

Educational Institution: Presidency University, Bangalore

Country: India

Full adder using basic gates

Full adder using basic gates
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Exp2_1

Exp2_1
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Verification of Logic Gates1

Verification of Logic Gates1
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exp 1 LEVEL 1

exp 1 LEVEL 1
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exp 1 LEVEL 1

exp 1 LEVEL 1
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Ansh Sir1

Ansh Sir1
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Verification of Logic Gates1

Verification of Logic Gates1
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Exp1Lev2

Exp1Lev2
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ansh2

ansh2
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Exp1Lev2

Exp1Lev2
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ansh exp2

ansh exp2
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ansh2

ansh2
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Exp1Lev2_Original

Exp1Lev2_Original
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ansh2

ansh2
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Untitled

Untitled
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half adder using basic gates

half adder using basic gates
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Full adder using basic gates

Full adder using basic gates
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Exp1Lev2

Exp1Lev2
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Untitled

Untitled
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Exp7

Exp7
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Experiment 2 Level 1: By using basic logic and XOR gates(2-bit Half Adder and Subtractor)

Experiment 2 Level 1: By using basic logic and XOR gates(2-bit Half Adder and Subtractor)
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