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Revanth Adithya Vanka

Member since: 1 year

Educational Institution: Not Entered

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Basic Gates

Basic Gates
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Half adder and half subtractor

Half adder and half subtractor
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FULL SUBTRACTOR

FULL SUBTRACTOR
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HAlf ADDER AND HALF SUBRACTOR USING NAND GATES

HAlf ADDER AND HALF SUBRACTOR USING NAND GATES
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FULL ADDER USING NAND

FULL ADDER USING NAND
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EXP 4 PRIORITY ENCODER

EXP 4 PRIORITY ENCODER
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EXP 3

EXP 3
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EXP 2 FULL ADDER

EXP 2 FULL ADDER
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Untitled

Untitled
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decoder

decoder
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Untitled

Untitled
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8:3 Encoder

8:3 Encoder
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4:1 MUX

4:1 MUX
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1:4 DeMUX

1:4 DeMUX
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NAND Implementation

NAND Implementation
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Transformation of NOR and NAND gates into basic logic gates

Transformation of NOR and NAND gates into basic logic gates
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4:1 MUX

4:1 MUX
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1:4 DeMUX

1:4 DeMUX
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NAND Implementation

NAND Implementation
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8:3 Encoder

8:3 Encoder
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