Bharathwaj V
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4:1 AND 1:4 MUX AND DEMUX
4:1 AND 1:4 MUX AND DEMUX
Half adder and Half Subtractor
Half adder and Half Subtractor
full adder and subtractor
full adder and subtractor
Experiment 5
Experiment 5
4-Bit Synchronous Up Counter
4-Bit Synchronous Up Counter
full adder and full subtractor
full adder and full subtractor
DEMUX 1:2
DEMUX 1:2
4:1 AND 1:4 MUX AND DEMUX
4:1 AND 1:4 MUX AND DEMUX
Untitled
Untitled
experiment 5 level 2
experiment 5 level 2
ADDERS AND SUBTRACTORS USING NAND1
ADDERS AND SUBTRACTORS USING NAND1
DEMUX 1:8
DEMUX 1:8
All Basic Gates
All Basic Gates
basic gates using universal gates(nor)
basic gates using universal gates(nor)
SR Flip Flop
SR Flip Flop
Construction of basic gates using Nand
Construction of basic gates using Nand
1 BIT COMPARATOR
1 BIT COMPARATOR
half adder and subtractor using xor and and gates
half adder and subtractor using xor and and gates
MUX AND DEMUXES
MUX AND DEMUXES
ENCODERS AND DECODERS
ENCODERS AND DECODERS
2 Bit comparator
2 Bit comparator
JK Flip Flop
JK Flip Flop
D To JK Flip Flop Conversion
D To JK Flip Flop Conversion
D Flip Flop
D Flip Flop
JK To D Flip Flop Conversion
JK To D Flip Flop Conversion
3 bit asynchronous up counter
3 bit asynchronous up counter
3 bit asynchronous down counter
3 bit asynchronous down counter
EXPT 5 LEVEL 1
EXPT 5 LEVEL 1
3 bit asynchronous up counter
3 bit asynchronous up counter
T Flip Flop
T Flip Flop
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