Member since: 9 months
Educational Institution: Presidency University, Bangalore
Country: India
EXP-7 3-BIT UP COUNTER USING JK FLIP FLOP
EXP-7 3-BIT UP COUNTER USING JK FLIP FLOPEXP-3,L-1,2DEMUX USING BASIC AND NAND GATES
EXP-3,L-1,2DEMUX USING BASIC AND NAND GATESEXP-3 L-1,2 MUX USING BASICAND NAND GATES
EXP-3 L-1,2 MUX USING BASICAND NAND GATESEXP-4 L-1 4:2 BIT BINARY ENCODER
EXP-4 L-1 4:2 BIT BINARY ENCODEREXP-4 L-1 2:4 DECODER
EXP-4 L-1 2:4 DECODEREXP-4 L-2 4:2 PRIORITY ENCODER
EXP-4 L-2 4:2 PRIORITY ENCODEREXP-3 L-2 1:4 DEMUX USING NAND GATES
EXP-3 L-2 1:4 DEMUX USING NAND GATESBASIC GATES EXP-1LEVEL-1
BASIC GATES EXP-1LEVEL-1BASIC GATE EXP-1 LEVEL-2
BASIC GATE EXP-1 LEVEL-2EXP-2L-1HALF ADDER/SUBTRACTOR
EXP-2L-1HALF ADDER/SUBTRACTOREXP-2 L-1 3-BIT FULL ADDER
EXP-2 L-1 3-BIT FULL ADDEREXP-2 L-2 HALF ADDER USING NAND GATE
EXP-2 L-2 HALF ADDER USING NAND GATEEXP-2 L-1 3-BIT FULL SUBTRACTOR
EXP-2 L-1 3-BIT FULL SUBTRACTOREXP-3-LEVEL-1
EXP-3-LEVEL-1EXP-6 L-1 , FLIP-FLOPS
EXP-6 L-1 , FLIP-FLOPSEXP-6,L-2,CONERTIONS USING FLIPFLOP
EXP-6,L-2,CONERTIONS USING FLIPFLOPEXP-2L-2 HALF SUBTRACTOR USING NAND GATE
EXP-2L-2 HALF SUBTRACTOR USING NAND GATEEXP-2 L-2 3-BIT FULL SUBTRACTOR USING GATE
EXP-2 L-2 3-BIT FULL SUBTRACTOR USING GATEEXP-2 L-2:3-BIT FULL ADDER USING NAND GATE
EXP-2 L-2:3-BIT FULL ADDER USING NAND GATEEXP-5 L-1 USING LOGIC GATES
EXP-5 L-1 USING LOGIC GATESEXP-5 L-1 USING NAND GATES
EXP-5 L-1 USING NAND GATESEXP-5 L-2 USING LOGIC GATES
EXP-5 L-2 USING LOGIC GATESEXP-5 L-2 USING NAND GATE
EXP-5 L-2 USING NAND GATEEXP-6 L-2 , FLIP-FLOPS USING NAND GATES
EXP-6 L-2 , FLIP-FLOPS USING NAND GATESCOUNTERS
COUNTERSEXP-7 4-BIT COUNTER USING TFF
EXP-7 4-BIT COUNTER USING TFFEXP-8 3-BIT ASYNCHRONOUS UP-COUNTER USING TFF
EXP-8 3-BIT ASYNCHRONOUS UP-COUNTER USING TFF