prajwal.v - Circuits

prajwal.v

Member since: 11 months

Educational Institution: Presidency University, Bangalore

Country: India

Untitled

Untitled

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AND gates

AND gates

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OR gate

OR gate

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NOT gate

NOT gate

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EXOR gate

EXOR gate

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NOR gate

NOR gate

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EX-NOR gate

EX-NOR gate

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NAND gate

NAND gate

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IMPLEMENTATION OF BASIC GATES USING NAND GATE:-

IMPLEMENTATION OF BASIC GATES USING NAND GATE:-

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HALF ADDER USING X-OR & NAND

HALF ADDER USING X-OR & NAND

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FULL ADDER

FULL ADDER

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HALF SUBTRACTOR USING X - OR AND NAND

HALF SUBTRACTOR USING X - OR AND NAND

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FULL SUBTRACTOR

FULL SUBTRACTOR

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HALF ADDER USING NAND ONLY

HALF ADDER USING NAND ONLY

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HALF SUBTRACTOR USING NAND ONLY

HALF SUBTRACTOR USING NAND ONLY

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FULL ADDER USING NAND ONLY

FULL ADDER USING NAND ONLY

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FULL SUBTRACTOR USING NAND ONLY

FULL SUBTRACTOR USING NAND ONLY

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2:1 MUX

2:1 MUX

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REALIZATION OF 4:1 MUX USING BASIC GATES AND XOR GATE

REALIZATION OF 4:1 MUX USING BASIC GATES AND XOR GATE

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1:2 DEMUX

1:2 DEMUX

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1:4 DE - MULTIPLEXER

1:4 DE - MULTIPLEXER

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USING UNIVERSAL GATE 2:1 MUX USING NAND

USING UNIVERSAL GATE 2:1 MUX USING NAND

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4:1 MUX USING NAND

4:1 MUX USING NAND

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4:1 MUX USING NAND

4:1 MUX USING NAND

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1:4 DEMUX USING NAND

1:4 DEMUX USING NAND

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2:1 DEMUX

2:1 DEMUX

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EXPERIMENT 2 LEVEL 1

EXPERIMENT 2 LEVEL 1

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EXPERIMENT 2 LEVEL 1

EXPERIMENT 2 LEVEL 1

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EXPERIMENT 3 LEVEL 1

EXPERIMENT 3 LEVEL 1

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EXPERIMENT 2 LEVEL 2

EXPERIMENT 2 LEVEL 2

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EXPERIMENT 2 LEVEL 2

EXPERIMENT 2 LEVEL 2

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EXPERIMENT 3 LEVEL 1

EXPERIMENT 3 LEVEL 1

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EXPERIMENT 3 LEVEL 2

EXPERIMENT 3 LEVEL 2

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EXPERIMENT 3 LEVEL 2

EXPERIMENT 3 LEVEL 2

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exp1/1

exp1/1

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EXP-2 LVL 1

EXP-2 LVL 1

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EXP 2 LEVEL 2

EXP 2 LEVEL 2

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MUX-DEMUX USING GATES

MUX-DEMUX USING GATES

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MUX-DEMUX USING NAND ONLY

MUX-DEMUX USING NAND ONLY

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EXAMPLE Abar C + Bbar C

EXAMPLE Abar C + Bbar C

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Experiment 5 L1

Experiment 5 L1

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Experiment 5 L2

Experiment 5 L2

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REALIZATION OF 2:1 MUX USING BASIC AND XOR GATE

REALIZATION OF 2:1 MUX USING BASIC AND XOR GATE

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