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mux using 8:1
mux using 8:1MUX using SOP
MUX using SOPMUX using POS 22BCE2797
MUX using POS 22BCE2797HS 4X1 MUX 22BKT0156
HS 4X1 MUX 22BKT0156T2 HA 4:1 MUX
T2 HA 4:1 MUXHalf Subtractor
Half SubtractorSOP using MUX
SOP using MUX3*3 Multiplier
3*3 MultiplierHalf Subtractor
Half SubtractorUntitled
UntitledTASK 2 03 L43+L44 4x4 Multiplier
TASK 2 03 L43+L44 4x4 Multiplier3*3 Multiplier
3*3 MultiplierUntitled
Untitled3x3 multiplier
3x3 multiplierPISO SHIFT REGISTER
PISO SHIFT REGISTERPISO
PISOUntitled
UntitledUntitled
UntitledUntitled
Untitledq3b1_2
q3b1_2CAT 2 Q3 B1
CAT 2 Q3 B1q1b2_2
q1b2_2UntitledCAT2B1Q5
UntitledCAT2B1Q5CAT 2 Q5 B1
CAT 2 Q5 B1q3b2_2
q3b2_2CAT2 Q4 B2
CAT2 Q4 B2q5b2_2
q5b2_2CAT2 Q5 B2
CAT2 Q5 B2NAND 3312
NAND 3312Half Adder Task 2
Half Adder Task 2Half Adder Task 2
Half Adder Task 2Full Adder Task 2
Full Adder Task 2Full Subtractor Task 2
Full Subtractor Task 2Half Subtractor Task 2
Half Subtractor Task 2Untitled
UntitledUntitled
UntitledTASK 1 DSD
TASK 1 DSDTASK 1 DSD
TASK 1 DSDTASK 1 DSD POS
TASK 1 DSD POSTASK 1 DSD POS NOR Gate
TASK 1 DSD POS NOR GateTASK 1 DSD POS NOR Gate
TASK 1 DSD POS NOR GateTASK 1 DSD SOP Using AND Gate
TASK 1 DSD SOP Using AND GateUntitled
Untitled4x1 MUX Viva
4x1 MUX Viva8x1 MUX VIVA
8x1 MUX VIVA8x1 MUX 2 VIVA
8x1 MUX 2 VIVA4x1 MUX 2 Viva
4x1 MUX 2 Viva1 Bit ALU Task 3 22BCE2797
1 Bit ALU Task 3 22BCE2797SOP canonical expression of MUX and circuit implemented in MUX
SOP canonical expression of MUX and circuit implemented in MUX3 bit ODD parity VIVA q1 Karen Joseph Williams 22BCE2797
3 bit ODD parity VIVA q1 Karen Joseph Williams 22BCE2797Decoder 1 Viva q2 Karen Joseph Williams
Decoder 1 Viva q2 Karen Joseph WilliamsUntitled
UntitledDecoder 2 Viva q2 Karen Joseph Williams 22BCE2797
Decoder 2 Viva q2 Karen Joseph Williams 22BCE2797Multiplexer 1 Viva q2 Karen Joseph Williams 22BCE2797
Multiplexer 1 Viva q2 Karen Joseph Williams 22BCE27973*8 DECODER USING TWO 2*4 DECODERS
3*8 DECODER USING TWO 2*4 DECODERSUntitled
UntitledSISO SHIFT REGISTER
SISO SHIFT REGISTERSIPO SHIFT REGISTER
SIPO SHIFT REGISTERDecoder
DecoderDecoder based design
Decoder based design2:1 MUX
2:1 MUXOdd bit Parity VIVA Karen 22BCE2797
Odd bit Parity VIVA Karen 22BCE2797CAT 1 Q1 B2
CAT 1 Q1 B2q2b1_2
q2b1_2Untitled
UntitledCAT2 Q2 B1
CAT2 Q2 B1CAT 2 Q1 B2
CAT 2 Q1 B2CAT2 Q3 B2
CAT2 Q3 B2Untitled
Untitledq4b2_2
q4b2_2Untitled
UntitledCAT 1 Q2
CAT 1 Q2CAT1 B2
CAT1 B2CAT1 B1
CAT1 B1T5 Cat 1 Q4 22BCE2797
T5 Cat 1 Q4 22BCE2797CAT 1 Q2 B2
CAT 1 Q2 B2CAT 1 Q4 B2
CAT 1 Q4 B2q4b1_2
q4b1_2CAT 2 Q4 B1
CAT 2 Q4 B1PIPO
PIPOPIPO Shift Register
PIPO Shift RegisterBidirectional Shift Register
Bidirectional Shift RegisterUntitled
UntitledHALF SUBTRACTOR USING 4:1 MUX
HALF SUBTRACTOR USING 4:1 MUXPos Canonical Expression in MUX
Pos Canonical Expression in MUXHalf Subtractor using MUX
Half Subtractor using MUXHALF ADDER USING 4:1 MUX
HALF ADDER USING 4:1 MUXPos Canonical Expression in MUX
Pos Canonical Expression in MUXBCD:3312
BCD:33123312 Multiplexer
3312 Multiplexer3312 Decoder
3312 Decoder3312 Demultiplexer
3312 DemultiplexerNOR 3312
NOR 3312Multiplexer 2 Viva q2 Karen Joseph Williams 22BCE2797
Multiplexer 2 Viva q2 Karen Joseph Williams 22BCE27978:3 Encoder
8:3 Encoder8:3 Encoder
8:3 Encoder7 segment display using 1:16 decoder
7 segment display using 1:16 decoder