project.name

Karen Joseph Williams

Member since: 1 year

Educational Institution: Not Entered

Country: Not Entered

mux using 8:1

mux using 8:1
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MUX using SOP

MUX using SOP
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MUX using POS 22BCE2797

MUX using POS 22BCE2797
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HS 4X1 MUX 22BKT0156

HS 4X1 MUX 22BKT0156
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T2 HA 4:1 MUX

T2 HA 4:1 MUX
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Half Subtractor

Half Subtractor
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SOP using MUX

SOP using MUX
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3*3 Multiplier

3*3 Multiplier
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Half Subtractor

Half Subtractor
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Untitled

Untitled
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TASK 2 03 L43+L44 4x4 Multiplier

TASK 2 03 L43+L44 4x4 Multiplier
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3*3 Multiplier

3*3 Multiplier
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Untitled

Untitled
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3x3 multiplier

3x3 multiplier
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PISO SHIFT REGISTER

PISO SHIFT REGISTER
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PISO

PISO
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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q3b1_2

q3b1_2
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CAT 2 Q3 B1

CAT 2 Q3 B1
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q1b2_2

q1b2_2
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UntitledCAT2B1Q5

UntitledCAT2B1Q5
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CAT 2 Q5 B1

CAT 2 Q5 B1
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q3b2_2

q3b2_2
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CAT2 Q4 B2

CAT2 Q4 B2
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q5b2_2

q5b2_2
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CAT2 Q5 B2

CAT2 Q5 B2
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NAND 3312

NAND 3312
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Half Adder Task 2

Half Adder Task 2
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Half Adder Task 2

Half Adder Task 2
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Full Adder Task 2

Full Adder Task 2
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Full Subtractor Task 2

Full Subtractor Task 2
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Half Subtractor Task 2

Half Subtractor Task 2
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Untitled

Untitled
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8:3 Encoder

8:3 Encoder
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Untitled

Untitled
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TASK 1 DSD

TASK 1 DSD
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TASK 1 DSD

TASK 1 DSD
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TASK 1 DSD POS

TASK 1 DSD POS
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TASK 1 DSD POS NOR Gate

TASK 1 DSD POS NOR Gate
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TASK 1 DSD POS NOR Gate

TASK 1 DSD POS NOR Gate
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TASK 1 DSD SOP Using AND Gate

TASK 1 DSD SOP Using AND Gate
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Untitled

Untitled
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8:3 Encoder

8:3 Encoder
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4x1 MUX Viva

4x1 MUX Viva
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8x1 MUX VIVA

8x1 MUX VIVA
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8x1 MUX 2 VIVA

8x1 MUX 2 VIVA
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4x1 MUX 2 Viva

4x1 MUX 2 Viva
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1 Bit ALU Task 3 22BCE2797

1 Bit ALU Task 3 22BCE2797
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SOP canonical expression of MUX and circuit implemented in MUX

SOP canonical expression of MUX and circuit implemented in MUX
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3 bit ODD parity VIVA q1 Karen Joseph Williams 22BCE2797

3 bit ODD parity VIVA q1 Karen Joseph Williams 22BCE2797
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Decoder 1 Viva q2 Karen Joseph Williams

Decoder 1 Viva q2 Karen Joseph Williams
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Untitled

Untitled
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Decoder 2 Viva q2 Karen Joseph Williams 22BCE2797

Decoder 2 Viva q2 Karen Joseph Williams 22BCE2797
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Multiplexer 1 Viva q2 Karen Joseph Williams 22BCE2797

Multiplexer 1 Viva q2 Karen Joseph Williams 22BCE2797
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3*8 DECODER USING TWO 2*4 DECODERS

3*8 DECODER USING TWO 2*4 DECODERS
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7 segment display using 1:16 decoder

7 segment display using 1:16 decoder
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Untitled

Untitled
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SISO SHIFT REGISTER

SISO SHIFT REGISTER
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SIPO SHIFT REGISTER

SIPO SHIFT REGISTER
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Decoder

Decoder
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Decoder based design

Decoder based design
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2:1 MUX

2:1 MUX
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Odd bit Parity VIVA Karen 22BCE2797

Odd bit Parity VIVA Karen 22BCE2797
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CAT 1 Q1 B2

CAT 1 Q1 B2
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q2b1_2

q2b1_2
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Untitled

Untitled
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CAT2 Q2 B1

CAT2 Q2 B1
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CAT 2 Q1 B2

CAT 2 Q1 B2
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CAT2 Q3 B2

CAT2 Q3 B2
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Untitled

Untitled
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q4b2_2

q4b2_2
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Untitled

Untitled
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CAT 1 Q2

CAT 1 Q2
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CAT1 B2

CAT1 B2
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CAT1 B1

CAT1 B1
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T5 Cat 1 Q4 22BCE2797

T5 Cat 1 Q4 22BCE2797
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CAT 1 Q2 B2

CAT 1 Q2 B2
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CAT 1 Q4 B2

CAT 1 Q4 B2
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q4b1_2

q4b1_2
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CAT 2 Q4 B1

CAT 2 Q4 B1
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PIPO

PIPO
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PIPO Shift Register

PIPO Shift Register
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Bidirectional Shift Register

Bidirectional Shift Register
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Untitled

Untitled
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HALF SUBTRACTOR USING 4:1 MUX

HALF SUBTRACTOR USING 4:1 MUX
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Pos Canonical Expression in MUX

Pos Canonical Expression in MUX
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Half Subtractor using MUX

Half Subtractor using MUX
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HALF ADDER USING 4:1 MUX

HALF ADDER USING 4:1 MUX
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Pos Canonical Expression in MUX

Pos Canonical Expression in MUX
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BCD:3312

BCD:3312
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3312 Multiplexer

3312 Multiplexer
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3312 Decoder

3312 Decoder
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3312 Demultiplexer

3312 Demultiplexer
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NOR 3312

NOR 3312
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Multiplexer 2 Viva q2 Karen Joseph Williams 22BCE2797

Multiplexer 2 Viva q2 Karen Joseph Williams 22BCE2797
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