T1 25 L43+L44 22BCE2904 POS F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')

cat2 b2 q1

CAT2 B2 Q3

CAT 2 B2 Q3

CAT1 B2 Q2

CAT1 B2 Q3

CAT B1 Q1

CAT 2 B1 Q3

Half Adder

Full Adder

Half Subtractor

Full Subtractor

3*3 Multiplier

T1 25 L43+L44 22BCE2904 Naman Agrawal F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BD

T1 25 L43+L44 22BCE2904 Naman Agrawal SOP Circuit F=Σm( 0,2,4,9,11,12,14 )=A’B’D’+A’C’D’+AB’D+ABD’

T1 25 L43+L44 22BCE2904 POS NOR F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')

Q7

Q16

Circuit diagram of 2:1 MUX Circuit using POS Equation --- NOR circuit

Pos Canonical Expression in MUX

Circuit diagram of 2:1 MUX Circuit using POS Equation --- OAI circuit

Circuit diagram of 2:1 MUX Circuit using SOP Equation --- NAND circuit

B1 CAT1 Q2

CAT2 B2 Q2

CAT2 B2 Q2

cat2 b2 q5

Circuit diagram for 3 bit even parity checker

Decoder 22BCE2904

(x'y'z')+(xyz')Decoder Based design 22BCE2904

(x'y'z')+(x+y+z') 22BCE2904 Multiplexer

1 BIT alu

30_22BCE3117_1Bit_ALU

4 BIT ALU

FS 8:1 MUX 22BKT0156

F POS decoder

Ha decoder

FADECODER 22BKT0156

HS using Decoder

FA using Decoder

HS using Decoder

HS usiing Decoder

f sop using decoder

HS 4X1 MUX 22BKT0156

HS 4X1 MUX 22BKT0156

Half Subtractor MUX

T2 HA 4:1 MUX

FS 4:1 MUX 22BKT0156

Half Subtractor using MUX

Untitled

NAND logic circuit of 2:4 decoder 03 22BCE0220 L43+L44

NAND logic circuit of 2:4 decoder 25 22BCE2904L43+L44

AOI logic circuit of 4:2 encoder 03 22BCE0220 L43+L44

Untitled

1:2 Decoder using Mux

SOPBCD3321

DA Q3 POS (OAI)

BCDMUX

BCDPOSOAI

DA QUES 3 DECODER

BCDDecoder

DA Q3 NOR

8:1 MUX USING 4:1 25 22BCE2904

Untitled

4:1 MUX using 2:1 MUX 22BCE2904 25

8:1 MUX using 4:1 MUX & 2:1 MUX

Question 1 DSD

Bidirectional Shift Register

Bidirectional shift register 22BCE2904 24

Synchronous 4 bit up down counter

Ring Counter 22BCE2904 24

Johnson 24 22BCE2904

CAT2 B2 Q5

Decoder

3 Bit Even Parity Checker 22BCE2904 Naman Agrawal

1:2 Decoder using Mux

CAT2 B1 Q5

question 8 part A

CAT1B1Q3

CAT 1 Q3 B1

CAT 1 Q4 B1

cat1 b1 q5

CAT1 B1 Q5

Cat2 B2 Q1

CAT2 B2 Q4

CAT2 B2 Q4

B1 CAT1 Q1

B1 CAT1 Q1

CAT1 B2 Q1

cat1b2q1

cat1b2q3

B2 Q4 CAT1

cat1b2q5

CAT-I Q4 B2

cat2 b1 q2

CAT2 B1 Q4

cat2b1q4

CAT2 B1 Q3

CAT1 B2 Q5

cat2b1q1

CAT2 B1 Q5

DA QUES3 MUX

SOPBCD

DA Q3 NOR

DA QUES 3 DEMUX

DA Q3 NAND

BCDNOR

BCDDEmux

BCDNAND

T1 25 L43+L44 22BCE2904 Naman Agrawal POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)

T1 25 L43+L44 22BCE2904 POS NAND F(0,2,4,9,11,12,14)=A’B’D’+A’C’D’+AB’D+ABD’

T1 25 L43+L44 22BCE2904 SOP NAND F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BD

T1 25 L43+L44 22BCE2904 POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)

4 bit Johnson Counter

cat2b1q2

(x+y')(x'+y)(z')Multiplexer based design 22BCE2904

Circuit diagram of 2:1 MUX Circuit using SOP Equation -- AOI circuit

AOI logic circuit of 4:2 encode25 22BCE2904 L43+L44

NAND logic circuit of 4:2 encoder 03 22BCE0220 L43+L44

30_22BCE3117_4Bit ALU

7 Seg Decoder

AOI logic circuit of 2:4 decoder 03 22BCE0220 L43+L44

Half Adder using Mux

4 Bit Adder