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T1 25 L43+L44 22BCE2904 POS F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')
T1 25 L43+L44 22BCE2904 POS F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')cat2 b2 q1
cat2 b2 q1CAT2 B2 Q3
CAT2 B2 Q3CAT 2 B2 Q3
CAT 2 B2 Q3CAT1 B2 Q2
CAT1 B2 Q2CAT1 B2 Q3
CAT1 B2 Q3CAT B1 Q1
CAT B1 Q1CAT 2 B1 Q3
CAT 2 B1 Q3Half Adder
Half AdderFull Adder
Full AdderHalf Subtractor
Half SubtractorFull Subtractor
Full Subtractor3*3 Multiplier
3*3 MultiplierT1 25 L43+L44 22BCE2904 Naman Agrawal F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BD
T1 25 L43+L44 22BCE2904 Naman Agrawal F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BDT1 25 L43+L44 22BCE2904 POS NOR F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')
T1 25 L43+L44 22BCE2904 POS NOR F=πM( 1,3,5,6,7,8,10,13,15) = (A'+B+D)(A+B'+C')(A+D')(B'+D')Q7
Q7Q16
Q16Pos Canonical Expression in MUX
Pos Canonical Expression in MUXCircuit diagram of 2:1 MUX Circuit using SOP Equation --- NAND circuit
Circuit diagram of 2:1 MUX Circuit using SOP Equation --- NAND circuitB1 CAT1 Q2
B1 CAT1 Q2CAT2 B2 Q2
CAT2 B2 Q2CAT2 B2 Q2
CAT2 B2 Q2cat2 b2 q5
cat2 b2 q5Circuit diagram for 3 bit even parity checker
Circuit diagram for 3 bit even parity checkerDecoder 22BCE2904
Decoder 22BCE2904(x'y'z')+(xyz')Decoder Based design 22BCE2904
(x'y'z')+(xyz')Decoder Based design 22BCE2904(x'y'z')+(x+y+z') 22BCE2904 Multiplexer
(x'y'z')+(x+y+z') 22BCE2904 Multiplexer1 BIT alu
1 BIT alu30_22BCE3117_1Bit_ALU
30_22BCE3117_1Bit_ALU4 BIT ALU
4 BIT ALUFS 8:1 MUX 22BKT0156
FS 8:1 MUX 22BKT0156F POS decoder
F POS decoderHa decoder
Ha decoderFADECODER 22BKT0156
FADECODER 22BKT0156HS using Decoder
HS using DecoderFA using Decoder
FA using DecoderHS using Decoder
HS using DecoderHS usiing Decoder
HS usiing Decoderf sop using decoder
f sop using decoderHS 4X1 MUX 22BKT0156
HS 4X1 MUX 22BKT0156HS 4X1 MUX 22BKT0156
HS 4X1 MUX 22BKT0156Half Subtractor MUX
Half Subtractor MUXT2 HA 4:1 MUX
T2 HA 4:1 MUXFS 4:1 MUX 22BKT0156
FS 4:1 MUX 22BKT0156Half Subtractor using MUX
Half Subtractor using MUXUntitled
UntitledNAND logic circuit of 2:4 decoder 03 22BCE0220 L43+L44
NAND logic circuit of 2:4 decoder 03 22BCE0220 L43+L44NAND logic circuit of 2:4 decoder 25 22BCE2904L43+L44
NAND logic circuit of 2:4 decoder 25 22BCE2904L43+L44Untitled
Untitled1:2 Decoder using Mux
1:2 Decoder using MuxSOPBCD3321
SOPBCD3321DA Q3 POS (OAI)
DA Q3 POS (OAI)BCDMUX
BCDMUXBCDPOSOAI
BCDPOSOAIDA QUES 3 DECODER
DA QUES 3 DECODERBCDDecoder
BCDDecoderDA Q3 NOR
DA Q3 NOR8:1 MUX USING 4:1 25 22BCE2904
8:1 MUX USING 4:1 25 22BCE2904Untitled
Untitled4:1 MUX using 2:1 MUX 22BCE2904 25
4:1 MUX using 2:1 MUX 22BCE2904 258:1 MUX using 4:1 MUX & 2:1 MUX
8:1 MUX using 4:1 MUX & 2:1 MUXQuestion 1 DSD
Question 1 DSDBidirectional Shift Register
Bidirectional Shift RegisterBidirectional shift register 22BCE2904 24
Bidirectional shift register 22BCE2904 24Ring Counter 22BCE2904 24
Ring Counter 22BCE2904 24Johnson 24 22BCE2904
Johnson 24 22BCE2904CAT2 B2 Q5
CAT2 B2 Q5Decoder
Decoder3 Bit Even Parity Checker 22BCE2904 Naman Agrawal
3 Bit Even Parity Checker 22BCE2904 Naman Agrawal1:2 Decoder using Mux
1:2 Decoder using MuxCAT2 B1 Q5
CAT2 B1 Q5question 8 part A
question 8 part ACAT1B1Q3
CAT1B1Q3CAT 1 Q3 B1
CAT 1 Q3 B1CAT 1 Q4 B1
CAT 1 Q4 B1cat1 b1 q5
cat1 b1 q5CAT1 B1 Q5
CAT1 B1 Q5Cat2 B2 Q1
Cat2 B2 Q1CAT2 B2 Q4
CAT2 B2 Q4CAT2 B2 Q4
CAT2 B2 Q4B1 CAT1 Q1
B1 CAT1 Q1B1 CAT1 Q1
B1 CAT1 Q1CAT1 B2 Q1
CAT1 B2 Q1cat1b2q1
cat1b2q1cat1b2q3
cat1b2q3B2 Q4 CAT1
B2 Q4 CAT1cat1b2q5
cat1b2q5CAT-I Q4 B2
CAT-I Q4 B2cat2 b1 q2
cat2 b1 q2CAT2 B1 Q4
CAT2 B1 Q4cat2b1q4
cat2b1q4CAT2 B1 Q3
CAT2 B1 Q3CAT1 B2 Q5
CAT1 B2 Q5cat2b1q1
cat2b1q1CAT2 B1 Q5
CAT2 B1 Q5DA QUES3 MUX
DA QUES3 MUXSOPBCD
SOPBCDDA Q3 NOR
DA Q3 NORDA QUES 3 DEMUX
DA QUES 3 DEMUXDA Q3 NAND
DA Q3 NANDBCDNOR
BCDNORBCDDEmux
BCDDEmuxBCDNAND
BCDNANDT1 25 L43+L44 22BCE2904 POS NAND F(0,2,4,9,11,12,14)=A’B’D’+A’C’D’+AB’D+ABD’
T1 25 L43+L44 22BCE2904 POS NAND F(0,2,4,9,11,12,14)=A’B’D’+A’C’D’+AB’D+ABD’T1 25 L43+L44 22BCE2904 SOP NAND F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BD
T1 25 L43+L44 22BCE2904 SOP NAND F’=Σm( 1,3,5,6,7,8,10,13,15 ) = AB’D’+A’BC+A’D+BDT1 25 L43+L44 22BCE2904 POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)
T1 25 L43+L44 22BCE2904 POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)4 bit Johnson Counter
4 bit Johnson Counter(x+y')(x'+y)(z')Multiplexer based design 22BCE2904
(x+y')(x'+y)(z')Multiplexer based design 22BCE2904Circuit diagram of 2:1 MUX Circuit using SOP Equation -- AOI circuit
Circuit diagram of 2:1 MUX Circuit using SOP Equation -- AOI circuitAOI logic circuit of 4:2 encode25 22BCE2904 L43+L44
AOI logic circuit of 4:2 encode25 22BCE2904 L43+L44NAND logic circuit of 4:2 encoder 03 22BCE0220 L43+L44
NAND logic circuit of 4:2 encoder 03 22BCE0220 L43+L4430_22BCE3117_4Bit ALU
30_22BCE3117_4Bit ALU7 Seg Decoder
7 Seg DecoderCircuit diagram of 2:1 MUX Circuit using POS Equation --- NOR circuit
Circuit diagram of 2:1 MUX Circuit using POS Equation --- NOR circuitAOI logic circuit of 2:4 decoder 03 22BCE0220 L43+L44
AOI logic circuit of 2:4 decoder 03 22BCE0220 L43+L44Circuit diagram of 2:1 MUX Circuit using POS Equation --- OAI circuit
Circuit diagram of 2:1 MUX Circuit using POS Equation --- OAI circuitHalf Adder using Mux
Half Adder using Mux4 Bit Adder
4 Bit AdderSynchronous 4 bit up down counter
Synchronous 4 bit up down counterT1 25 L43+L44 22BCE2904 Naman Agrawal SOP Circuit F=Σm( 0,2,4,9,11,12,14 )=A’B’D’+A’C’D’+AB’D+ABD’
T1 25 L43+L44 22BCE2904 Naman Agrawal SOP Circuit F=Σm( 0,2,4,9,11,12,14 )=A’B’D’+A’C’D’+AB’D+ABD’AOI logic circuit of 4:2 encoder 03 22BCE0220 L43+L44
AOI logic circuit of 4:2 encoder 03 22BCE0220 L43+L44cat2b1q2
cat2b1q2T1 25 L43+L44 22BCE2904 Naman Agrawal POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)
T1 25 L43+L44 22BCE2904 Naman Agrawal POS F’=πM( 0,2,4,9,11,12,14) = (A+B+D)(A+C+D)(A’+B+D’)(A’+B’+D)