Bidirectional Shift Register

VIVA Q2

Task2_Half_Adder

Task II Full Adder

Task II Half Subtrator

Task II Full Subtractor

Task II 4-Bit Adder

Task II 2x2 Multiplier

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TASK1 F'(POS) NOR Implementation

Task1 F'(SOP) NAND Impementation

4 Bit ALU

PIPO Shift Register

SIPO Shift Register

PIPO Shift Register

random counter

cat2 B1 q2

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Task 1 SOP Active Low Logic

B1_Q5

B2_Q2

B2_Q4

B2_Q5

SISO Shift Register

B1_Q2

Full Adder Using 4:1 MUX

2:1 Multiplexer circuit using NOR logic

Task 1 POS Active High Logic

1Bit ALU

POS_MUX

DA QUES3 MUX

DA Q3 POS (OAI)

DA QUES 3 DECODER

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Task 1 using decoder SOP

Task 1 using 4:16 Decoder POS

Task 1 Multiplexer

2:1 MUX NOR IMPLEMENTATION

2:1 MUX NAND IMPLEMENTATION

Half Adder using 4:1 MUX

Half Adder using 4:1 MUX

Half Subtractor using 4:1 MUX

Task 1 using 8:1 MUX

Full adder using 8:1 MUX

Full Subtractor using 4:1 MUX

Full adder using 8:1 MUX

Full Subtractor using 8:1 MUX

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B1_Q3

B2_Q1

Mod N Counter

DA Q3 NAND

DA Q3 NOR

DA Q3 POS (OAI)

DA QUES 3 DEMUX

2:1 MUX POS OAI