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Full Adder using 4:1 MUX
Full Adder using 4:1 MUXCAT 2 B2 Q3
CAT 2 B2 Q3CAT 2 B2 Q5
CAT 2 B2 Q5HA
HAHS
HSFA
FAFS
FS3*3 multi
3*3 multi2*2 multi
2*2 multi4*4 multi
4*4 multi4 Bit adder
4 Bit adderf sop nand
f sop nandf sop nor
f sop norf' sop nor
f' sop norf' sop nand
f' sop nandf pos nor
f pos norf pos nand
f pos nandf sop
f sopf sop
f sopf sop
f sopf' sop
f' sopf pos nand
f pos nandf' pos
f' pos4 Bit SISO Shift Register
4 Bit SISO Shift Register4 Bit SIPO Shift Register
4 Bit SIPO Shift Register4 BIT PISO SHIFT REGISTER
4 BIT PISO SHIFT REGISTER4 Bit PIPO Shift Register
4 Bit PIPO Shift RegisterCAT 1 B2 Q1
CAT 1 B2 Q1BCD to 4321 using NOR Logic with dc
BCD to 4321 using NOR Logic with dcBCD to 4321 using NAND logic with dc
BCD to 4321 using NAND logic with dc4 BIT ALU NIT
4 BIT ALU NITBCD to 4321 without dc
BCD to 4321 without dcNAND logic circuit of 2:4 Decoder
NAND logic circuit of 2:4 DecoderAOI logic circuit of 2:4 Decoder
AOI logic circuit of 2:4 DecoderAOI logic circuit of 4:2 encoder
AOI logic circuit of 4:2 encoderNAND logic circuit of 4:2 encoder
NAND logic circuit of 4:2 encoderF SOP using decoder
F SOP using decoderF POS using Decoder
F POS using DecoderHalf adder using Decoder
Half adder using Decoder4:1 MUX using AOI
4:1 MUX using AOICAT 1 B1 Q2
CAT 1 B1 Q2f' pos nand
f' pos nand8:1 MUX A - SL
8:1 MUX A - SL8:1 MUX B - SL
8:1 MUX B - SLFull Subtractor using 8:1 MUX
Full Subtractor using 8:1 MUX4:1 MUX SOP
4:1 MUX SOP4:1 MUX POS
4:1 MUX POSHalf Adder using 4:1 MUX
Half Adder using 4:1 MUXHalf Subtractor using 4:1 MUX
Half Subtractor using 4:1 MUXFull Subtractor using 4:1 MUX
Full Subtractor using 4:1 MUX2:1 MUX POS
2:1 MUX POSFull Adder using 8:1 MUX
Full Adder using 8:1 MUXPOS MUX Circuit
POS MUX Circuit2:1 MUX SOP
2:1 MUX SOPSOP MUX Circuit
SOP MUX Circuit2:1 MUX NAND
2:1 MUX NAND2:1 MUX NOR
2:1 MUX NOR16:1 MUX SOP
16:1 MUX SOP16:1 MUX POS
16:1 MUX POSFull adder using Decoder
Full adder using DecoderHalf subtractor using Decoder
Half subtractor using DecoderFull subtractor using Decoder
Full subtractor using DecoderFull Adder USING FA
Full Adder USING FAfull adder
full adderf' pos nor
f' pos nordecoder
decoderCAT 2 B1 Q5
CAT 2 B1 Q5CAT 2 B2 Q1
CAT 2 B2 Q1Bidirectional Shift Register
Bidirectional Shift RegisterMOD 10 Counter
MOD 10 CounterCAT 1 B1 Q1
CAT 1 B1 Q1CAT I B1 Q4
CAT I B1 Q4CAT 1 B2 Q4
CAT 1 B2 Q4CAT 2 B2 Q4
CAT 2 B2 Q4CAT-2 B2 Q5
CAT-2 B2 Q5f' sop nor
f' sop norf pos
f posBCD to 4321 POS without dc
BCD to 4321 POS without dcBCD to 4321 using MUX with Don't Care
BCD to 4321 using MUX with Don't CareBCD to 4321 using DeMultiplexer with Don't Care
BCD to 4321 using DeMultiplexer with Don't CareBCD to 4321 using Decoder with Don't Care
BCD to 4321 using Decoder with Don't CareCAT 1 B2 Q2
CAT 1 B2 Q2CAT 1 B2 Q5
CAT 1 B2 Q5Decoder Task 2
Decoder Task 2BCD to 4321 using AOI Logic with Don't Care
BCD to 4321 using AOI Logic with Don't CareBCD to 4321 using OAI Logic with Don't Care
BCD to 4321 using OAI Logic with Don't CareCAT 1 B1 Q5
CAT 1 B1 Q54 BIT ALU
4 BIT ALUbcd to gray code converter using 16x1 mux
bcd to gray code converter using 16x1 muxCAT 2 B1 Q3
CAT 2 B1 Q3