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Yashasvi Verma 22BCE2504

Member since: 1 year

Educational Institution: VIT VELLORE

Country: India

random counter

random counter
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3 bit synchronous up/down counter using T flipflop

3 bit synchronous up/down counter using T flipflop
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RANDON counter

RANDON counter
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MOD n counter

MOD n counter
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4 -BIT Adder

4 -BIT Adder
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Mux for (b) y1

Mux for (b) y1
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Mux for (b) y1

Mux for (b) y1
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Mux for (B) y2

Mux for (B) y2
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Full Adder

Full Adder
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Half Subtractor

Half Subtractor
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Full Subtractor

Full Subtractor
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SOP expression Using MUX

SOP expression Using MUX
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4:1 Mux Using 2:1 Mux

4:1 Mux Using 2:1 Mux
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8:1 USING 4:1

8:1 USING 4:1
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Multiplexer Based Circuit Using 8:1 MUX

Multiplexer Based Circuit Using 8:1 MUX
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AOI logic circuit of 2:4 Decoder

AOI logic circuit of 2:4 Decoder
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NAND logic circuit of 2:4 Decoder

NAND logic circuit of 2:4 Decoder
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NAND logic circuit of 4:2 encoder

NAND logic circuit of 4:2 encoder
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Task I (SOP) implemented using Decoder Active Low logic

Task I (SOP) implemented using Decoder Active Low logic
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POS Expression Using MUX

POS Expression Using MUX
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Homework Q18

Homework Q18
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Q2 java 2

Q2 java 2
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q2 dsd 1

q2 dsd 1
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1 BIT ALU

1 BIT ALU
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7 Segment Decoder common cathode

7 Segment Decoder common cathode
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Task I (POS) implemented using Decoder Active High logic

Task I (POS) implemented using Decoder Active High logic
Public
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Circuit verse link for code convertor circuit using NAND logic

Circuit verse link for code convertor circuit using NAND logic
Public
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Circuit verse link for code convertor circuit using NOR logic

Circuit verse link for code convertor circuit using NOR logic
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Hot Question 2 mux (a)

Hot Question 2 mux (a)
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SISO SIPO

SISO SIPO
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PISO PIPO

PISO PIPO
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Bi-Directional Shift Registers

Bi-Directional Shift Registers
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CAT-1 Q1

CAT-1 Q1
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CAT-1 Q2

CAT-1 Q2
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CAT-1 Q4

CAT-1 Q4
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CAT1 Q5

CAT1 Q5
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CAT1 Q1 B2

CAT1 Q1 B2
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CAT1 B2 Q2

CAT1 B2 Q2
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Binary to 7 Segment

Binary to 7 Segment
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Q3_2_2

Q3_2_2
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Untitled

Untitled
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Untitled

Untitled
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CAT1 B2 Q4

CAT1 B2 Q4
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Half Adder

Half Adder
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CAT1 B2 Q5

CAT1 B2 Q5
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CAT2 B1 Q3

CAT2 B1 Q3
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CAT2 B1 Q5

CAT2 B1 Q5
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CAT2 B2 Q1

CAT2 B2 Q1
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CAT2 B2 Q3

CAT2 B2 Q3
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CAT2 B2 Q4

CAT2 B2 Q4
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DA Q9_1

DA Q9_1
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DA Q9_2

DA Q9_2
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7 segment display using 1:16 demux

7 segment display using 1:16 demux
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Q9_3 DA

Q9_3 DA
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7 segment display using 4:16 decoder

7 segment display using 4:16 decoder
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7 segment display using 3:8 decoder

7 segment display using 3:8 decoder
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CAT2 B2 Q5

CAT2 B2 Q5
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Circuit vese code convertor circuit link using Multiplexer

Circuit vese code convertor circuit link using Multiplexer
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Circuit vese code convertor circuit link using Demultiplexer

Circuit vese code convertor circuit link using Demultiplexer
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CAT2 B1 Q4

CAT2 B1 Q4
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CAT2 B2 Q2

CAT2 B2 Q2
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AOI Logic Circuit

AOI Logic Circuit
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Decoder for reg. no.

Decoder for reg. no.
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Mux for reg. no.

Mux for reg. no.
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Circuit Diagram Using 2:1 MUX NOR

Circuit Diagram Using 2:1 MUX NOR
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4 BIT ADDER

4 BIT ADDER
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Viva Q1

Viva Q1
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Hot Question 2 dec (a)

Hot Question 2 dec (a)
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CAT 2 B1 Q4

CAT 2 B1 Q4
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da q8 a

da q8 a
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q8 da b

q8 da b
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7 Seg Decoder COMMON ANODE

7 Seg Decoder COMMON ANODE
Public
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DA 3_2_2

DA 3_2_2
Public
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Binary to 7 Segment COMMON ANODE

Binary to 7 Segment COMMON ANODE
Public
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7 Seg Decoder COMMON CATHODE

7 Seg Decoder COMMON CATHODE
Public
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DA 3_1_1

DA 3_1_1
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random counter

random counter
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Circuit Diagram Using 2:1 MUX NAND

Circuit Diagram Using 2:1 MUX NAND
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Multiplexer based circuit implemented using 4:1 Multiplexer

Multiplexer based circuit implemented using 4:1 Multiplexer
Public
project.name

Circuit vese code convertor circuit link using OAI logic

Circuit vese code convertor circuit link using OAI logic
Public
project.name

AOI logic circuit

AOI logic circuit
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Circuit Diagram Using 2:1 MUX AOI

Circuit Diagram Using 2:1 MUX AOI
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Binary to 7 Segment

Binary to 7 Segment
Public
project.name

Task I (POS) implemented using Decoder Active Low logic

Task I (POS) implemented using Decoder Active Low logic
Public
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cat 2 b1 q2

cat 2 b1 q2
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7 segment display 1:16 demux using 1:8 demux

7 segment display 1:16 demux using 1:8 demux
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project.name

Task I (SOP) implemented using Decoder Active High logic

Task I (SOP) implemented using Decoder Active High logic
Public
project.name

DA Q6

DA Q6
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7 segment display using 3:8 decoder

7 segment display using 3:8 decoder
Public
project.name

AOI logic circuit of 4:2 encoder

AOI logic circuit of 4:2 encoder
Public
project.name

Circuit verse link for code convertor circuit using AOI logic

Circuit verse link for code convertor circuit using AOI logic
Public
project.name

Circuit vese code convertor circuit link using Decoder

Circuit vese code convertor circuit link using Decoder
Public
project.name

7 segment display using 1:16 demux

7 segment display using 1:16 demux
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16:1 USING 8:1

16:1 USING 8:1
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7 segment display using 4:16 decoder

7 segment display using 4:16 decoder
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Circuit Diagram Using POS equation OAI

Circuit Diagram Using POS equation OAI
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