NAND logic circuit of 4:2 encoder

HALF ADDER USING DECODER

F SOP using decoder

full adder using decoder

HAlf adder using decoder

Half subtractor using decoder

TASK 2 HALF ADDER

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Task1 SOP

Task1

2:1 MUX Circuit using POS Equation --- NOR circuit

1 BIT ALU

CAT-1 Q2

CAT-1 Q5 B2

CAT-1 B1 Q3

4-Bit Shift Register (RS)

CAT-1 B1 Q4

Q5 CAT-2 B1

Q3 CAT-2 B2

4-Bit Shift Register using D Flip-Flops

PISO SHIFT REGISTER

Task II implemented using 4:1 Multiplexer

AOI logic circuit of 2:4 Decoder

AOI logic circuit of 2:4 Decoder

AOI logic circuit of 4:2 encoder

2:1 SOP AOI

2:1 MUX Circuit using POS

4 Bit ALU

Task I implemented using 16:1 Multiplexer

8:1 Multiplexer

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AOI Logic

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Decoder

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PAL

PLA

PAL

Control CPLD

CPLD

FPGA

ttl

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Asynchronous Ripple Counter

TTL LOGIC

Decoder

4 to 16 decoder

4x16 decoder

3X8 DECODER

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random counter

Full Subtractor using 3 to 8 Decoder

4 bit SIPO Shift Register

CAT-1 Q1

Bidirectional Shift Register

q4 CAT1

BINARY TO GRAY CODE CONVERTER

B2 CAT1 1

CAT-1 B2 Q2

CAT-1 B2 Q4

3 BIT MAGNITUDE COMPARATOR

SISO shift register

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OAI

NAND logic circuit of 2:4 Decoder

AOI logic circuit of 4:2 encoder

AOI logic circuit of 4:2 encoder1

NAND logic circuit of 4:2 encoder

Shift Register - PIPO Mode

Full subtractor using decoder

booth multiplication

MOD 11 ASYNCHRONOUS COUNTER

NAND logic circuit of 2:4 Decoder

2:1 MUX Circuit using SOP Equation --- NAND circuit

Synchronous counter 3 bit up counter using D-Flip flop

JK To T Flip Flop Conversion

4 BIT ALU