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NAND logic circuit of 4:2 encoder
NAND logic circuit of 4:2 encoderHALF ADDER USING DECODER
HALF ADDER USING DECODERF SOP using decoder
F SOP using decoderfull adder using decoder
full adder using decoderHAlf adder using decoder
HAlf adder using decoderHalf subtractor using decoder
Half subtractor using decoderTASK 2 HALF ADDER
TASK 2 HALF ADDERUntitled
UntitledTask1 SOP
Task1 SOPTask1
Task12:1 MUX Circuit using POS Equation --- NOR circuit
2:1 MUX Circuit using POS Equation --- NOR circuit1 BIT ALU
1 BIT ALUCAT-1 Q2
CAT-1 Q2CAT-1 Q5 B2
CAT-1 Q5 B2CAT-1 B1 Q3
CAT-1 B1 Q34-Bit Shift Register (RS)
4-Bit Shift Register (RS)CAT-1 B1 Q4
CAT-1 B1 Q4JK To T Flip Flop Conversion
JK To T Flip Flop ConversionQ5 CAT-2 B1
Q5 CAT-2 B1Q3 CAT-2 B2
Q3 CAT-2 B24-Bit Shift Register using D Flip-Flops
4-Bit Shift Register using D Flip-FlopsPISO SHIFT REGISTER
PISO SHIFT REGISTERTask II implemented using 4:1 Multiplexer
Task II implemented using 4:1 MultiplexerAOI logic circuit of 2:4 Decoder
AOI logic circuit of 2:4 DecoderAOI logic circuit of 2:4 Decoder
AOI logic circuit of 2:4 DecoderAOI logic circuit of 4:2 encoder
AOI logic circuit of 4:2 encoder2:1 SOP AOI
2:1 SOP AOI2:1 MUX Circuit using POS
2:1 MUX Circuit using POS4 BIT ALU
4 BIT ALU4 Bit ALU
4 Bit ALUTask I implemented using 16:1 Multiplexer
Task I implemented using 16:1 Multiplexer8:1 Multiplexer
8:1 MultiplexerUntitled
UntitledUntitled
UntitledAOI Logic
AOI LogicUntitled
UntitledDecoder
DecoderUntitled
UntitledPAL
PALPLA
PLAPAL
PALControl CPLD
Control CPLDCPLD
CPLDFPGA
FPGAttl
ttlUntitled
UntitledUntitled
UntitledUntitled
UntitledUntitled
UntitledUntitled
UntitledAsynchronous Ripple Counter
Asynchronous Ripple CounterTTL LOGIC
TTL LOGICDecoder
Decoder4 to 16 decoder
4 to 16 decoder4x16 decoder
4x16 decoder3X8 DECODER
3X8 DECODERUntitled
Untitledrandom counter
random counterFull Subtractor using 3 to 8 Decoder
Full Subtractor using 3 to 8 Decoder4 bit SIPO Shift Register
4 bit SIPO Shift RegisterCAT-1 Q1
CAT-1 Q1Bidirectional Shift Register
Bidirectional Shift Registerq4 CAT1
q4 CAT1BINARY TO GRAY CODE CONVERTER
BINARY TO GRAY CODE CONVERTERB2 CAT1 1
B2 CAT1 1CAT-1 B2 Q2
CAT-1 B2 Q2CAT-1 B2 Q4
CAT-1 B2 Q43 BIT MAGNITUDE COMPARATOR
3 BIT MAGNITUDE COMPARATORSISO shift register
SISO shift registerUntitled
UntitledUntitled
UntitledOAI
OAINAND logic circuit of 2:4 Decoder
NAND logic circuit of 2:4 DecoderAOI logic circuit of 4:2 encoder
AOI logic circuit of 4:2 encoderAOI logic circuit of 4:2 encoder1
AOI logic circuit of 4:2 encoder1NAND logic circuit of 4:2 encoder
NAND logic circuit of 4:2 encoderShift Register - PIPO Mode
Shift Register - PIPO ModeFull subtractor using decoder
Full subtractor using decoderbooth multiplication
booth multiplicationMOD 11 ASYNCHRONOUS COUNTER
MOD 11 ASYNCHRONOUS COUNTERNAND logic circuit of 2:4 Decoder
NAND logic circuit of 2:4 Decoder2:1 MUX Circuit using SOP Equation --- NAND circuit
2:1 MUX Circuit using SOP Equation --- NAND circuitSynchronous counter 3 bit up counter using D-Flip flop
Synchronous counter 3 bit up counter using D-Flip flop