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Ujjwal Agrawal 22BCE3784

Member since: 1 year

Educational Institution: Not Entered

Country: Not Entered

NAND logic circuit of 4:2 encoder

NAND logic circuit of 4:2 encoder
Public
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HALF ADDER USING DECODER

HALF ADDER USING DECODER
Public
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F SOP using decoder

F SOP using decoder
Public
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full adder using decoder

full adder using decoder
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HAlf adder using decoder

HAlf adder using decoder
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Half subtractor using decoder

Half subtractor using decoder
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TASK 2 HALF ADDER

TASK 2 HALF ADDER
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Untitled

Untitled
Public
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Task1 SOP

Task1 SOP
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Task1

Task1
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2:1 MUX Circuit using POS Equation --- NOR circuit

2:1 MUX Circuit using POS Equation --- NOR circuit
Public
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1 BIT ALU

1 BIT ALU
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CAT-1 Q2

CAT-1 Q2
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CAT-1 Q5 B2

CAT-1 Q5 B2
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CAT-1 B1 Q3

CAT-1 B1 Q3
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4-Bit Shift Register (RS)

4-Bit Shift Register (RS)
Public
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CAT-1 B1 Q4

CAT-1 B1 Q4
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JK To T Flip Flop Conversion

JK To T Flip Flop Conversion
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Q5 CAT-2 B1

Q5 CAT-2 B1
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Q3 CAT-2 B2

Q3 CAT-2 B2
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4-Bit Shift Register using D Flip-Flops

4-Bit Shift Register using D Flip-Flops
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PISO SHIFT REGISTER

PISO SHIFT REGISTER
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Task II implemented using 4:1 Multiplexer

Task II implemented using 4:1 Multiplexer
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AOI logic circuit of 2:4 Decoder

AOI logic circuit of 2:4 Decoder
Public
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AOI logic circuit of 2:4 Decoder

AOI logic circuit of 2:4 Decoder
Public
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AOI logic circuit of 4:2 encoder

AOI logic circuit of 4:2 encoder
Public
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2:1 SOP AOI

2:1 SOP AOI
Public
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2:1 MUX Circuit using POS

2:1 MUX Circuit using POS
Public
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4 BIT ALU

4 BIT ALU
Public
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4 Bit ALU

4 Bit ALU
Public
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Task I implemented using 16:1 Multiplexer

Task I implemented using 16:1 Multiplexer
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8:1 Multiplexer

8:1 Multiplexer
Public
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Untitled

Untitled
Public
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Untitled

Untitled
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AOI Logic

AOI Logic
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Untitled

Untitled
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Decoder

Decoder
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Untitled

Untitled
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PAL

PAL
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PLA

PLA
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PAL

PAL
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Control CPLD

Control CPLD
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CPLD

CPLD
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FPGA

FPGA
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ttl

ttl
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Untitled

Untitled
Public
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Untitled

Untitled
Public
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Untitled

Untitled
Public
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Untitled

Untitled
Public
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Untitled

Untitled
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Asynchronous Ripple Counter

Asynchronous Ripple Counter
Public
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TTL LOGIC

TTL LOGIC
Public
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Decoder

Decoder
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4 to 16 decoder

4 to 16 decoder
Public
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4x16 decoder

4x16 decoder
Public
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3X8 DECODER

3X8 DECODER
Public
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Untitled

Untitled
Public
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random counter

random counter
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Full Subtractor using 3 to 8 Decoder

Full Subtractor using 3 to 8 Decoder
Public
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4 bit SIPO Shift Register

4 bit SIPO Shift Register
Public
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CAT-1 Q1

CAT-1 Q1
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Bidirectional Shift Register

Bidirectional Shift Register
Public
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q4 CAT1

q4 CAT1
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BINARY TO GRAY CODE CONVERTER

BINARY TO GRAY CODE CONVERTER
Public
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B2 CAT1 1

B2 CAT1 1
Public
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CAT-1 B2 Q2

CAT-1 B2 Q2
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CAT-1 B2 Q4

CAT-1 B2 Q4
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3 BIT MAGNITUDE COMPARATOR

3 BIT MAGNITUDE COMPARATOR
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SISO shift register

SISO shift register
Public
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Untitled

Untitled
Public
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Untitled

Untitled
Public
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OAI

OAI
Public
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NAND logic circuit of 2:4 Decoder

NAND logic circuit of 2:4 Decoder
Public
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AOI logic circuit of 4:2 encoder

AOI logic circuit of 4:2 encoder
Public
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AOI logic circuit of 4:2 encoder1

AOI logic circuit of 4:2 encoder1
Public
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NAND logic circuit of 4:2 encoder

NAND logic circuit of 4:2 encoder
Public
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Shift Register - PIPO Mode

Shift Register - PIPO Mode
Public
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Full subtractor using decoder

Full subtractor using decoder
Public
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booth multiplication

booth multiplication
Public
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MOD 11 ASYNCHRONOUS COUNTER

MOD 11 ASYNCHRONOUS COUNTER
Public
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NAND logic circuit of 2:4 Decoder

NAND logic circuit of 2:4 Decoder
Public
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2:1 MUX Circuit using SOP Equation --- NAND circuit

2:1 MUX Circuit using SOP Equation --- NAND circuit
Public
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Synchronous counter 3 bit up counter using D-Flip flop

Synchronous counter 3 bit up counter using D-Flip flop
Public
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