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Divyansh Singh

Member since: 1 year

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2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44

2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44
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2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44

2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44
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8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44

8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44
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Full adder using Decoder 03 22BCE0220 L43+L44

Full adder using Decoder 03 22BCE0220 L43+L44
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SOP Decoder

SOP Decoder
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Decoder using the SOP 03 22BCE0220 L43+L44

Decoder using the SOP 03 22BCE0220 L43+L44
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FULL ADDER TASK 2

FULL ADDER TASK 2
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HALF ADDER TASK 2

HALF ADDER TASK 2
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Untitled

Untitled
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2X2 MULTIPLIER TASK 2

2X2 MULTIPLIER TASK 2
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Untitled

Untitled
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Untitled

Untitled
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Circuit diagram using NAND gate

Circuit diagram using NAND gate
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TASK 1 OAI

TASK 1 OAI
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DA QUES 3 DECODER

DA QUES 3 DECODER
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DA Q3 POS (OAI)

DA Q3 POS (OAI)
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DA QUES3 MUX

DA QUES3 MUX
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DA QUES 3 DEMUX

DA QUES 3 DEMUX
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DA Q3 NAND

DA Q3 NAND
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DA Q3 NOR

DA Q3 NOR
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Untitled

Untitled
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2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44

2:1 MUX using the SOP NAND equation 03 22CE0220 L43+L44
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8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44

8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44
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8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44

8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44
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8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44

8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44
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8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44

8:1 Using The 4:1 MUX 03 22BCE0220 L43+L44
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POS using the 4:1 MUX 03 22BCE0220 L43+L44

POS using the 4:1 MUX 03 22BCE0220 L43+L44
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Decoder using the SOP 03 22BCE0220 L43+L44

Decoder using the SOP 03 22BCE0220 L43+L44
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SOP Decoder

SOP Decoder
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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SOP 16:1 MUX 03 22BCE0220 L43+L44

SOP 16:1 MUX 03 22BCE0220 L43+L44
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2:1 using the POS equation 03 22BCE0220 L43+L44

2:1 using the POS equation 03 22BCE0220 L43+L44
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POS using the 4:1 MUX 03 22BCE0220 L43+L44

POS using the 4:1 MUX 03 22BCE0220 L43+L44
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SOP on the MUX 03 22BCE0220 L43+L44

SOP on the MUX 03 22BCE0220 L43+L44
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2:1 MUX using the SOP equation 03 22BCE0220 L43+L44

2:1 MUX using the SOP equation 03 22BCE0220 L43+L44
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2:1 using the POS equation 03 22BCE0220 L43+L44

2:1 using the POS equation 03 22BCE0220 L43+L44
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Untitled

Untitled
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POS using the 4:1 MUX 03 22BCE0220 L43+L44

POS using the 4:1 MUX 03 22BCE0220 L43+L44
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Decoder using the SOP 03 22BCE0220 L43+L44

Decoder using the SOP 03 22BCE0220 L43+L44
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Untitled

Untitled
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Untitled

Untitled
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TASK 1 OAI Logic Gates

TASK 1 OAI Logic Gates
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TASK 1 NAND Logic Gate

TASK 1 NAND Logic Gate
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Untitled

Untitled
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16:1 MUX

16:1 MUX
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16:1 Decoder

16:1 Decoder
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2:1 MUX using the POS NOR 03 22BCE0220 L43+L44

2:1 MUX using the POS NOR 03 22BCE0220 L43+L44
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SOP 16:1 MUX 03 22BCE0220 L43+L44

SOP 16:1 MUX 03 22BCE0220 L43+L44
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AOI DA

AOI DA
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Decoder using the SOP 03 22BCE0220 L43+L44

Decoder using the SOP 03 22BCE0220 L43+L44
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FULL SUBTRACTOR TASK 2

FULL SUBTRACTOR TASK 2
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DA Q3 SOP (AOI)

DA Q3 SOP (AOI)
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