project.name

Alex Bracamonte

Member since: 1 year

Educational Institution: Not Entered

Country: Not Entered

FSM_Moore_Counter 0 to 4

FSM_Moore_Counter 0 to 4
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FF SR

FF SR
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FF_JK_With_Scope

FF_JK_With_Scope
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FF type D with Scope

FF type D with Scope
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Untitled

Untitled
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CircuitClase1

CircuitClase1
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FF_JK_With_Scope

FF_JK_With_Scope
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Untitled

Untitled
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Asynchronous Counter

Asynchronous Counter
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Untitled

Untitled
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JK_Base

JK_Base
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Untitled

Untitled
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Circuit2

Circuit2
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MiniTerm to ROM

MiniTerm to ROM
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Untitled

Untitled
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Untitled

Untitled
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FSM_MooreExample

FSM_MooreExample
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Latch SR

Latch SR
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FSM_Moore_Example

FSM_Moore_Example
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3 variable adder

3 variable adder
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Latch SR

Latch SR
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Untitled

Untitled
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Inversor

Inversor
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Example Mux 16:1 using 4:1

Example Mux 16:1 using 4:1
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Divisor3bits

Divisor3bits
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Logic Gates with Verilog

Logic Gates with Verilog
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FSM_Elevador

FSM_Elevador
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Untitled

Untitled
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Dario4

Dario4
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Splitter

Splitter
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JK_Base

JK_Base
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FSM_MealyExample_Class

FSM_MealyExample_Class
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ParaleloASerie

ParaleloASerie
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Led2_FSM_Mealy

Led2_FSM_Mealy
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SAP - 1

SAP - 1
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Alex Bracamonte is not a collaborator of any project.

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