MD SAHID
Member since: 1 year
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sahid 2
sahid 2
Public
ex 2
ex 2
Public
sahid
sahid
Public
Experiment 5 level 1
Experiment 5 level 1
Public
Experiment 5 level 2
Experiment 5 level 2
Public
Experiment 5 level 1
Experiment 5 level 1
Public
Experiment 5 level 2
Experiment 5 level 2
Public
Experiment 5 level 1
Experiment 5 level 1
Public
experiment-2
experiment-2
Public
experiment3(2)
experiment3(2)
Public
Untitled
Untitled
Public
D to JK Flipflop
D to JK Flipflop
Public
jk flip flop implementation using NAND gate
jk flip flop implementation using NAND gate
Public
JK to D Flipflop conversion using circuit verse simulator
JK to D Flipflop conversion using circuit verse simulator
Public
Untitled no
Untitled no
Public
Untitled
Untitled
Public
4 Experiment Level 1
4 Experiment Level 1
Public
4 expriment level 2
4 expriment level 2
Public
qwer
qwer
Public
flipflop
flipflop
Public
Untitled
Untitled
Public
circuit diagram 4 EX-7
circuit diagram 4 EX-7
Public
active and low SRlatch
active and low SRlatch
Public
3 BIT Ex-7
3 BIT Ex-7
Public
ex 5
ex 5
Public
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