project.name

s.MeghanaReddy

Member since: 7 months

Educational Institution: presidency university

Country: India

experiment-4, 4:2 8:2

experiment-4, 4:2 8:2
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2:4 decoder

2:4 decoder
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3:8 decoder

3:8 decoder
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experiment-2 ,level-1

experiment-2 ,level-1
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experiment 2 (level 2)

experiment 2 (level 2)
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experiment 2 (level 2)

experiment 2 (level 2)
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Untitled

Untitled
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Untitled

Untitled
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project1

project1
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L-2 2:1 4:1 MUX

L-2 2:1 4:1 MUX
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L-1 1:2 1:4 demux

L-1 1:2 1:4 demux
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L-2 1:2 1:4 DEMUX

L-2 1:2 1:4 DEMUX
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L-1 halfadder and subtractor

L-1 halfadder and subtractor
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L-1 full adder and subtractor

L-1 full adder and subtractor
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full adder and full subtractor using xor and nand gates

full adder and full subtractor using xor and nand gates
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half adder and subtractor using nand gates

half adder and subtractor using nand gates
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Untitled

Untitled
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experiment 05

experiment 05
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Untitled

Untitled
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Synchronous 3-bit

Synchronous 3-bit
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L-1 2:1 4:1mux

L-1 2:1 4:1mux
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Experiment-6

Experiment-6
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half adder and subtractor using nand and xor gates

half adder and subtractor using nand and xor gates
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