Dishita H Gokuldas
Member since: 1 year
Educational Institution: Not Entered
Country: Not Entered
QUESTION 2
QUESTION 2
QUESTION 1
QUESTION 1
4:2 ENCODER
4:2 ENCODER
dishita circuits
dishita circuits
experiment number 1
experiment number 1
HALF SUBTRACTOR USING BSIC GATES
HALF SUBTRACTOR USING BSIC GATES
HALF SUBTRACTOR USING NAND GATES
HALF SUBTRACTOR USING NAND GATES
FULL SUBTRACTOR USING EX-OR AND BASIC GATES
FULL SUBTRACTOR USING EX-OR AND BASIC GATES
FULL SUBTRACTOR USING NAND GATES ONLY
FULL SUBTRACTOR USING NAND GATES ONLY
EXPERIMENT NUMBER2
EXPERIMENT NUMBER2
HALF ADDER USING EX-OR AND BASIC GATES
HALF ADDER USING EX-OR AND BASIC GATES
HALF ADDER USING NAND GATES
HALF ADDER USING NAND GATES
FULL ADDER USING EXOR
FULL ADDER USING EXOR
Untitled 2
Untitled 2
D FLIP FLOP
D FLIP FLOP
2 : 1 MUX Using Basic Gates
2 : 1 MUX Using Basic Gates
4:1 MUX
4:1 MUX
4:1 MUX USING BASIC GATES
4:1 MUX USING BASIC GATES
2:1 MUX
2:1 MUX
Record #5
Record #5
2 BIT UPCOUNTER USING T FF
2 BIT UPCOUNTER USING T FF
Untitled
Untitled
EXPERIMENT NUMBER2
EXPERIMENT NUMBER2
21SEPT
21SEPT
24AUG
24AUG
24AUG classwork
24AUG classwork
HALF ADDER USING EX-OR AND BASIC GATES
HALF ADDER USING EX-OR AND BASIC GATES
HALF ADDER USING NAND GATES
HALF ADDER USING NAND GATES
21sept
21sept
21SEP NAND GATES ONLY
21SEP NAND GATES ONLY
HALF ADDER USING EX-OR AND GATES
HALF ADDER USING EX-OR AND GATES
HALF ADDER USING NAND GATES
HALF ADDER USING NAND GATES
