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Snigdha Mullick

Member since: 1 year

Educational Institution: Not Entered

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Untitled 1

Untitled 1
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snigdha mullick circuits

snigdha mullick circuits
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experiment number 1

experiment number 1
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HALF SUBTRACTOR USING BASIC GATES

HALF SUBTRACTOR USING BASIC GATES
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UNTITLED 3

UNTITLED 3
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HALF SUBTRACTOR USING NAND GATES

HALF SUBTRACTOR USING NAND GATES
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FULL SUBTRACTOR USING EX-OR AND BASIC AGTES

FULL SUBTRACTOR USING EX-OR AND BASIC AGTES
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FULL SUBTRACTOR USING NAND GATES ONLY

FULL SUBTRACTOR USING NAND GATES ONLY
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EXPERIMENT NUMBER 2

EXPERIMENT NUMBER 2
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HALF ADDER USING EX-OR AND GATES

HALF ADDER USING EX-OR AND GATES
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HALF ADDER USING NAND GATES

HALF ADDER USING NAND GATES
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Full Adder using EXOR

Full Adder using EXOR
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experiment 3-diagrams

experiment 3-diagrams
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2:1 MUX using basic gates

2:1 MUX using basic gates
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12-10-2023

12-10-2023
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4:1 MUX

4:1 MUX
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2:1 MUX

2:1 MUX
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question 1

question 1
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question 2

question 2
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question 3

question 3
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question 4

question 4
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4:2 encoder

4:2 encoder
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8:3 encoder

8:3 encoder
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question 5

question 5
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T flip flop

T flip flop
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D flip flop

D flip flop
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JK flip flop

JK flip flop
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Untitled 2

Untitled 2
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experiment number 1

experiment number 1
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EXPERIMENT NUMBER2

EXPERIMENT NUMBER2
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EXPERIMENT NUMBER 2

EXPERIMENT NUMBER 2
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24AUG

24AUG
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24AUG classwork

24AUG classwork
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NOT,AND,OR,EX-OR

NOT,AND,OR,EX-OR
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classwork

classwork
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Classwork 17th AUG

Classwork 17th AUG
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21SEPT

21SEPT
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HALF ADDER USING NAND GATES

HALF ADDER USING NAND GATES
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Snigdha Mullick is not a collaborator of any project.

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