Y.LAKSHMI LAHARI
Member since: 11 months
Educational Institution: Not Entered
Country: India
4:2 ENCODER
4:2 ENCODER
Public
Untitled
Untitled
Public
Untitled
Untitled
Public
Untitled
Untitled
Public
verification of logic gates
verification of logic gates
Public
lahari
lahari
Public
LOGIC GATES
LOGIC GATES
Public
Untitled
Untitled
Public
logic circuit
logic circuit
Public
Untitled
Untitled
Public
HALF SUBTRACTOR
HALF SUBTRACTOR
Public
HALF SUBTRACTOR
HALF SUBTRACTOR
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HALF SUBTRACTOR USING NAND GATES
HALF SUBTRACTOR USING NAND GATES
Public
FULL SUBTRACTOR USING EXOR AND BASIC GATES
FULL SUBTRACTOR USING EXOR AND BASIC GATES
Public
HALF ADDER USING BASIC GATES
HALF ADDER USING BASIC GATES
Public
FULL SUBTRACTOR USING ONLY NAND GATE
FULL SUBTRACTOR USING ONLY NAND GATE
Public
HALF ADDER USING EX-OR anD AND GATE
HALF ADDER USING EX-OR anD AND GATE
Public
FULL ADDER USING EX-OR AND BASIC GATES
FULL ADDER USING EX-OR AND BASIC GATES
Public
Untitled
Untitled
Public
1:2 DEMUX
1:2 DEMUX
Public
D FLIP FLOP
D FLIP FLOP
Public
2:1 mux using basic gates
2:1 mux using basic gates
Public
2:1 mux
2:1 mux
Public
4:1 MUX USING BASIC GATES
4:1 MUX USING BASIC GATES
Public
4:1 MUX
4:1 MUX
Public
8:1 MUX
8:1 MUX
Public
4:1 MUX Q1
4:1 MUX Q1
Public
2 BIT UP COUNTER USING FLIPFLOP
2 BIT UP COUNTER USING FLIPFLOP
Public
DOWN COUNTER USING JK FF
DOWN COUNTER USING JK FF
Public
HALF ADDER USING NAND GATE
HALF ADDER USING NAND GATE
Public
logical gates
logical gates
Public
1:4 DE MUX
1:4 DE MUX
Public
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