4:2 ENCODER

Serial In Serial Out Shift Register

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24AUG

LAB01 3AUG Comp. Fundamental

Verification of logic gates

Class Work (Experiment No. 1) 17th AUG

17 Aug Ques self try

Full subtractor using only NAND Gates

Parallel In Parallel Out Shift Register

Difference and B_out using XOR and basic gates

Difference Using XOR and Basic Gates seperately

Difference using only basic gates

DIFFERENCE AND BORROW USING ONLY NAND GATES

Sum and carry

up

8:1 MULTIPLEX

1:2 DE MUX

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1:4 DE MUX BLOCK DIAGRAM

Random Expression DE MUX Block Diagram

Random Expression DE MUX Block Diagram

Random Expression DE MUX Block Diagram

Half Subtractor using NAND Gates

Half Adder using Basic Gates (2)

Full adder using only NAND Gates

Half Substractor Using XOR and Basic Gates

Half Substractor Using Basic Gates

Full Adder using EXOR and basic gates

Half Adder using only NAND gates

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Full subtractor using EXOR and basic gates

name

4:1 MUX

8:1 MUX

4:1 MUX

4:1 MUX SELF TRY

8:1 MUX SELF TRY

Class work 5 October

Class work 5 October

2:1 MUX using basic gates

4:1 MUX USING BASIC GATES

3bit DOWN counter using JK Flip Flop

3bit UP counter Flip Flop

4-bit Asynchronous UP Counter Using JK flip flop

Serial In Parallel Out Shift Register

4-bit Asynchronous DOWN counter using JK Flip Flop

Class Question

4-bit Asynchronous UP Counter Using JK flip flop

4-bit Asynchronous DOWN counter using JK Flip Flop