program 1

program 3

program 2

Set 6

program 5

Set 7

First lab.Gates

Half adder , Full adder

4*1 multiplexer

8*1 multiplexer

16*1 multiplexer

4*1 multiplexer

1*16 De-multiplexer

1*8 De-multiplexer

4 to 16 Decoder

3 to 8 Decoder

16 to 4 Encoder

8 to 3 Encoder

Half Subtractor

Full Subtractor

1*4 De-multiplexer

exam mid 1

LAB EXAM 2

4 to 2 Encoder

LAB EXAM 2

2 to 4 Decoder

implementation of And gate,Or gate,Not gate using Nand gate

program 4