FPGA with LUT and bus
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Author: Robin Hodson

Forked from: Robin Hodson/Previous recovered

Project access type: Public


A "trivial" FPGA, with two overall inputs, two overall outputs, and a 2/4 bit LUT with two output stages.

Forked from my initial test circuit, which originally revealed only the tri-state bug. So this is my second experiment.

Due to the tri-state bug and diodes not being currently (6th July 2023) supported by the simulator, I had to fudge the bus interface. Somehow got all that working, then starting running into the limits of the simulator again:

  1. Self-inverting loops are not allowed (such as could be used to self-generate clocks), because the simulator tries to solve the circuit absolutely rather than in stages, thus tying itself up in an infinite loop! This isn't much of an issue in this situation, as the self-generated clock configuration is a novelty. It's still a bug to raise though.
  2. Neither the second output stage of the LUT, nor the overall second output, can be configured as connected, because this exceeds the capacity of the simulator! To fix this, [a fork of] the circuit needs to be broken up into subcircuits. This is a good idea anyway, as there are numerous repeating blocks, particularly within the necessarily-overcomplicated bus.
I note that means I've built a simulator inside the simulator. This isn't a problem; if anything, it's a good system test/validation: Eg, if a C compiler can compile its own source code, it's probably mature software.

Created: Jul 05, 2023

Updated: Jul 05, 2023


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