Member since: 1 year
Educational Institution: presidency university
Country: India
Half Subtractor
Half SubtractorFULL SUBTRACTOR
FULL SUBTRACTORHalf adder using NAND
Half adder using NANDFull adder using NAND
Full adder using NAND2:1 MUX USING NAND
2:1 MUX USING NAND2:1 MUX
2:1 MUX4:1 MUX USING NAND
4:1 MUX USING NAND4:1 DEMUX USING NAND
4:1 DEMUX USING NAND2:4 DECODER
2:4 DECODER4:2 ENCODER
4:2 ENCODERUntitled
Untitled4:2 ENCODER
4:2 ENCODERENCODER
ENCODERExperiment 5 using basic gates
Experiment 5 using basic gatesExperiment 5 using NAND gates
Experiment 5 using NAND gates2 BIT COMPARATOR USING BASIC GATES
2 BIT COMPARATOR USING BASIC GATES4:1 DEMUX
4:1 DEMUXUNIVERSAL GATE IMPLEMENTATION USING NAND
UNIVERSAL GATE IMPLEMENTATION USING NANDJK FLIP FLOP USING NAND
JK FLIP FLOP USING NANDJK FLIP FLOP TO D FLIP FLOP
JK FLIP FLOP TO D FLIP FLOP2:1 DEMUX USING NAND
2:1 DEMUX USING NAND1 bit using Basic gate
1 bit using Basic gateFull Adder
Full AdderHalf adder
Half adderHalf subtractor using NAND
Half subtractor using NAND4:1 MUX
4:1 MUX2:1 DEMUX
2:1 DEMUXProblem solving 1 02 using basic gates
Problem solving 1 02 using basic gatesLOGIC GATES
LOGIC GATESFlip flop
Flip flop4 bit up down counter
4 bit up down counter3 bit up down counter
3 bit up down counterfull substractor
full substractorFull subtractor using NAND
Full subtractor using NAND