Experiment 5 using basic gates

Experiment 5 using NAND gates

1 bit using Basic gate

Half adder

Half Subtractor

FULL SUBTRACTOR

Half adder using NAND

Full adder using NAND

2:1 MUX

4:1 MUX

2:1 DEMUX

4:1 DEMUX

Problem solving 1 02 using basic gates

2:1 MUX USING NAND

2:1 DEMUX USING NAND

4:1 DEMUX USING NAND

LOGIC GATES

UNIVERSAL GATE IMPLEMENTATION USING NAND

4 BIT SYNCHRONOUS

3 BIT Synchronous counter

Flip flop

Half subtractor using NAND

JK FLIP FLOP USING NAND

JK FLIP FLOP TO D FLIP FLOP

2:4 DECODER

4:2 ENCODER

Untitled

4:2 ENCODER

ENCODER

Experiment 5 using basic gates

4:1 MUX USING NAND

Full subtractor using NAND

2 BIT COMPARATOR USING BASIC GATES

Full Adder

Problem solving 1 02 using NAND gates