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Author: Yaswanth raju
Project access type: Public
Description:
LEVEL:1
Logic gates of 2:1 MUX
4:1 MUX using basic gates
1:2 De MUX using basic gates
1:4 De MUX using using basic gates
LEVEL:2
2:1 MUX using Universal gates
4:1 MUX using NAND gates
1:2 DEMUX using NAND
1:4 DEMUX using NAND
Created: May 04, 2023
Updated: Aug 27, 2023
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