Lab Class 2

Lab Class 3

Lab Class 1

Lab Class 4

PRIORITY ENCODER

EXPERIMENT 15A

Full adder using NAND Gate

FULL SUBTRACTOR USING NAND GATE

HALF SUBTRACTOR USING NAND GATE

half adder using nand gates

4-1 Multiplexer

1-4 DE-MULTIPLEXER

4:2 priority encoder

4*1 USING NAND GATES

4:1 MUX implementation using NAND gates

1:2 DEMUX using NAND and 1:4 DEMUX using NAND

2*4 Decoder

2*4 Decoder

4:2 - bit Binary Encoder

Combinational logical circuit

Level 2 Exp-5

T FLIPFLOP

JK Flip-Flop

SR Latch

Experiment 6

D Flip FLop

D Flip Flop to J-K Flip Flop

JK Flip Flop

SR Flip Flop

SR-Latch

Lab 9

4 Bit Syncronous counter

3 BIT SYNCHRONOUS UP/DOWN COUNTER

2:1 Multiplexer

D flip-flop

2:1 Multiplexer using nand gates

1:4 Demultiplexer using logic gates

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