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Author: BAD-W D
Project access type: Public
Description:
implementing a clock squencial circuit from a state diagram.
state table:
P.S N.S output
x=0 x=1
Qa Qb Qa+ Qb+ Qa+ Qb+ x=0 x=1
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 1
1 1 1 0 1 1 0 0
Created: Mar 31, 2020
Updated: Jun 30, 2023
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