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ojas

Member since: 1 year

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Project 2

Project 2
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Registers

Registers
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SISO Registers

SISO Registers
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SIPO Register

SIPO Register
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SR To JK Flip Flop Conversion

SR To JK Flip Flop Conversion
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JK to T flip-flop

JK to T flip-flop
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JK to SR flip flop

JK to SR flip flop
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SR to JK flipflop

SR to JK flipflop
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Parallel Adder/Subtractor

Parallel Adder/Subtractor
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Clocked SR Flip Flop

Clocked SR Flip Flop
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Registers

Registers
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3 input majority circuit using decoder

3 input majority circuit using decoder
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MAJORITY CIRCUIT

MAJORITY CIRCUIT
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MAJORITY CIRCUIT

MAJORITY CIRCUIT
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21BKT0062-CAT1-Q4

21BKT0062-CAT1-Q4
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SR To JK Flip Flop Conversion

SR To JK Flip Flop Conversion
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JK To D Flip Flop Conversion

JK To D Flip Flop Conversion
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3 input majority circuit using 4X1 MUX

3 input majority circuit using 4X1 MUX
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2 bit comparator using basic gates

2 bit comparator using basic gates
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