Member since: 2 years
Educational Institution: Presidency Uiversity, Bangalore
Country: India
HALF SUBTRACTOR USING NAND GATES
HALF SUBTRACTOR USING NAND GATES1:2 DEMUX USING BASIC
1:2 DEMUX USING BASIC1:4 DEMUX USING NAND
1:4 DEMUX USING NAND1:2 DEMUX USING NAND
1:2 DEMUX USING NAND4:2 ENCODER
4:2 ENCODERexpriment 3 2:1 mux(nand)
expriment 3 2:1 mux(nand)EXPERIMENT 3 - 2:1 MULTIPLEXER
EXPERIMENT 3 - 2:1 MULTIPLEXERHALF SUBTRACTOR USING BASIC GATES
HALF SUBTRACTOR USING BASIC GATESUntitled
UntitledEXPERIMENT 5 LEVEL 2 BASIC GATES
EXPERIMENT 5 LEVEL 2 BASIC GATESEXPERIMENT 5 LEVEL 1 NAND GATES
EXPERIMENT 5 LEVEL 1 NAND GATESExperiment 3 4:1 MUX USING BASIC GATES
Experiment 3 4:1 MUX USING BASIC GATES4:2 ENCODER
4:2 ENCODER1:4 DEMUX USING BASIC
1:4 DEMUX USING BASIC1:4 DEMUX USING BASIC
1:4 DEMUX USING BASICFULL ADDER USING 3:8 DECODER
FULL ADDER USING 3:8 DECODERHALF ADDER USING 2:4 DECODER
HALF ADDER USING 2:4 DECODERSR FLIP FLOP USING NAND GATES
SR FLIP FLOP USING NAND GATESD FLIP FLOP USING NAND GATES
D FLIP FLOP USING NAND GATESJK FLIP FLOP USING NAND GATES
JK FLIP FLOP USING NAND GATEST FLIP FLOP USING NAND GATES
T FLIP FLOP USING NAND GATESExperiment 3 4:1 MUX using NAND gates
Experiment 3 4:1 MUX using NAND gates1:4 DEMUX USING BASIC
1:4 DEMUX USING BASIC3 Bit Asynchronous Down Counter
3 Bit Asynchronous Down Counter2:4 DECODER USING BASIC
2:4 DECODER USING BASICEXPERIMENT 5 LEVEL 2 NAND GATES
EXPERIMENT 5 LEVEL 2 NAND GATESFull adder using basic gates
Full adder using basic gates