project.name

Ander VM V M

Member since: 5 years

Educational Institution: Not Entered

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Unidad Aritmetica

Unidad Aritmetica
Public
project.name

Mux Circuito 1 2a1

Mux Circuito 1 2a1
Public
project.name

Mux Circuito 3 4a1

Mux Circuito 3 4a1
Public
project.name

Mux Circuito 2 2a1 R

Mux Circuito 2 2a1 R
Public
project.name

Mux 8a1

Mux 8a1
Public
project.name

Demux 1a4

Demux 1a4
Public
project.name

Demux 1 a 8

Demux 1 a 8
Public
project.name

Unidad Logica

Unidad Logica
Public
project.name

Circuito Aritmeticologica

Circuito Aritmeticologica
Public
project.name

Latches SR con Reloj

Latches SR con Reloj
Public
project.name

Latch Nor

Latch Nor
Public
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Latch D con reloj

Latch D con reloj
Public
project.name

Flip-flop D

Flip-flop D
Public
project.name

Biestable SR

Biestable SR
Public
project.name

Biestable SR Maestro-Esclavo

Biestable SR Maestro-Esclavo
Public
project.name

Biestable JK Por Flancos

Biestable JK Por Flancos
Public
project.name

Biestable D Retardado

Biestable D Retardado
Public
project.name

Memoria de 4 Palabras

Memoria de 4 Palabras
Public
project.name

Registro de 3 Bits

Registro de 3 Bits
Public
project.name

Contador 4 Bit

Contador 4 Bit
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

CPU

CPU
Public
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Unidad aritmética lógica con registros de entrada y salida

Unidad aritmética lógica con registros de entrada y salida
Public
project.name

Biestable tipo JK

Biestable tipo JK
Public
project.name

Contador programable ascendente/descendente de 4 bits

Contador programable ascendente/descendente de 4 bits
Public
project.name
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