AKSHAYA A
Member since: 1 year
Educational Institution: Presidency Uiversity, Bangalore
Country: India
4:2 Priority Encoder
4:2 Priority Encoder
Public
4:2 Priority encoder
4:2 Priority encoder
Public
Encoder and Decoder logic gates
Encoder and Decoder logic gates
Public
EXPERIMENT 7
EXPERIMENT 7
Public
Exp2 - 3bit (full) adder
Exp2 - 3bit (full) adder
Public
Exp-1
Exp-1
Public
Exp1
Exp1
Public
MUX using basic gates
MUX using basic gates
Public
DE Multiplexer
DE Multiplexer
Public
3bit Full adder using NAND gate
3bit Full adder using NAND gate
Public
3bit full subtractor usig nand gate
3bit full subtractor usig nand gate
Public
Exp - 5 (Combinational logic circuit)
Exp - 5 (Combinational logic circuit)
Public
JK to D flip flop conversion
JK to D flip flop conversion
Public
D to JK flip flop conversion (Exp - 6)
D to JK flip flop conversion (Exp - 6)
Public
Conversion of one FF to other
Conversion of one FF to other
Public
EXP8
EXP8
Public
2:1 MUX
2:1 MUX
Public
4:1 MUX
4:1 MUX
Public
Experiment-7
Experiment-7
Public
Exp2 (half adder)
Exp2 (half adder)
Public
Exp2 (half subtractor)
Exp2 (half subtractor)
Public
Exp1- Basic gates
Exp1- Basic gates
Public
Exp2- 3bit full subtractor
Exp2- 3bit full subtractor
Public
Design logic gates using NAND gates (exp-5)
Design logic gates using NAND gates (exp-5)
Public
Conversion of one FF to other
Conversion of one FF to other
Public
MUX using basic and XOR gate
MUX using basic and XOR gate
Public
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