project.name

Srilakshmi Kh

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

EXPT-1 L1 LOGICGATES

EXPT-1 L1 LOGICGATES
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LOGIC GATES

LOGIC GATES
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EXPT-1 LOGIC GATES

EXPT-1 LOGIC GATES
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EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES

EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES
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EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES

EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES
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4 BIT SYNCHRONOUS

4 BIT SYNCHRONOUS
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EXPT1

EXPT1
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HALF ADDER AND SUBTRACTOR USING NAND GATES

HALF ADDER AND SUBTRACTOR USING NAND GATES
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EXPT-2 6

EXPT-2 6
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expt-2 :5,6

expt-2 :5,6
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DISTRIBUTIVE

DISTRIBUTIVE
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ABORPTION LAW

ABORPTION LAW
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EXPT-2:1,2,3,4

EXPT-2:1,2,3,4
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FF CONVERSION

FF CONVERSION
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EXPT-3 MUX DEMUX

EXPT-3 MUX DEMUX
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ASYNCHRONOUS UP DOWN COUNTER-3BIT

ASYNCHRONOUS UP DOWN COUNTER-3BIT
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EXPT-6 LEVEL-1

EXPT-6 LEVEL-1
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expt-8 Asynchronous up/down counter

expt-8 Asynchronous up/down counter
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EXPT-5

EXPT-5
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EXPT-5

EXPT-5
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EXPT-1L1

EXPT-1L1
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EXPT-2 HALF ADDER/SUBTRACTOR

EXPT-2 HALF ADDER/SUBTRACTOR
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HALF ADDER AND FULL ADDER

HALF ADDER AND FULL ADDER
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MUX IMPLEMENTATION

MUX IMPLEMENTATION
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STUDY OF FLIP FLOPS

STUDY OF FLIP FLOPS
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EXPT-7-LEVEL1

EXPT-7-LEVEL1
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EXPT-7 NAND BASED JKFF AND DFF

EXPT-7 NAND BASED JKFF AND DFF
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STUDY OF FLIP FLOPS

STUDY OF FLIP FLOPS
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EXPT7-LEVEL2 FF CONVERSIONS

EXPT7-LEVEL2 FF CONVERSIONS
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LOGICAL IMPLEMENTATION

LOGICAL IMPLEMENTATION
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EXPT-7 NAND BASED JKFF AND DFF

EXPT-7 NAND BASED JKFF AND DFF
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4 BIT SYNCHRONOUS CIRCUIT

4 BIT SYNCHRONOUS CIRCUIT
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QUESNO12

QUESNO12
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EXPT-1 LEVEL2

EXPT-1 LEVEL2
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EXPT-1 LEVEL2

EXPT-1 LEVEL2
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EXPT-5 PART-1

EXPT-5 PART-1
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1BIT COMPARATOR

1BIT COMPARATOR
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EXPT-7 SYNCHRONOUS COUNTER

EXPT-7 SYNCHRONOUS COUNTER
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EXPT-4 ADDER

EXPT-4 ADDER
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3BIT ADDER / FULL ADDER

3BIT ADDER / FULL ADDER
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2 BIT COMPARATOR

2 BIT COMPARATOR
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LEVEL-2 BIT COMPARATOR

LEVEL-2 BIT COMPARATOR
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EXPT1-L2

EXPT1-L2
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EXPT-1 LEVEL1

EXPT-1 LEVEL1
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EXPT-1 LOGIC GATES

EXPT-1 LOGIC GATES
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EXPT-1 LEVEL2

EXPT-1 LEVEL2
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