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EXPT-1 L1 LOGICGATES
EXPT-1 L1 LOGICGATESLOGIC GATES
LOGIC GATESEXPT-1 LOGIC GATES
EXPT-1 LOGIC GATESEXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES
EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATESEXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES
EXPT-1 LEVEL2 BASIC GATES USING UNIVERSAL GATES4 BIT SYNCHRONOUS
4 BIT SYNCHRONOUSEXPT1
EXPT1HALF ADDER AND SUBTRACTOR USING NAND GATES
HALF ADDER AND SUBTRACTOR USING NAND GATESEXPT-2 6
EXPT-2 6expt-2 :5,6
expt-2 :5,6DISTRIBUTIVE
DISTRIBUTIVEABORPTION LAW
ABORPTION LAWEXPT-2:1,2,3,4
EXPT-2:1,2,3,4FF CONVERSION
FF CONVERSIONEXPT-3 MUX DEMUX
EXPT-3 MUX DEMUXASYNCHRONOUS UP DOWN COUNTER-3BIT
ASYNCHRONOUS UP DOWN COUNTER-3BITEXPT-6 LEVEL-1
EXPT-6 LEVEL-1expt-8 Asynchronous up/down counter
expt-8 Asynchronous up/down counterEXPT-5
EXPT-5EXPT-5
EXPT-5EXPT-1L1
EXPT-1L1EXPT1-L2
EXPT1-L2EXPT-2 HALF ADDER/SUBTRACTOR
EXPT-2 HALF ADDER/SUBTRACTORHALF ADDER AND FULL ADDER
HALF ADDER AND FULL ADDERMUX IMPLEMENTATION
MUX IMPLEMENTATIONSTUDY OF FLIP FLOPS
STUDY OF FLIP FLOPSEXPT-7-LEVEL1
EXPT-7-LEVEL1EXPT-7 NAND BASED JKFF AND DFF
EXPT-7 NAND BASED JKFF AND DFFSTUDY OF FLIP FLOPS
STUDY OF FLIP FLOPSEXPT7-LEVEL2 FF CONVERSIONS
EXPT7-LEVEL2 FF CONVERSIONSLOGICAL IMPLEMENTATION
LOGICAL IMPLEMENTATIONEXPT-7 NAND BASED JKFF AND DFF
EXPT-7 NAND BASED JKFF AND DFF4 BIT SYNCHRONOUS CIRCUIT
4 BIT SYNCHRONOUS CIRCUITQUESNO12
QUESNO12EXPT-1 LEVEL2
EXPT-1 LEVEL2EXPT-1 LEVEL2
EXPT-1 LEVEL2EXPT-5 PART-1
EXPT-5 PART-11BIT COMPARATOR
1BIT COMPARATOREXPT-7 SYNCHRONOUS COUNTER
EXPT-7 SYNCHRONOUS COUNTEREXPT-4 ADDER
EXPT-4 ADDER3BIT ADDER / FULL ADDER
3BIT ADDER / FULL ADDER2 BIT COMPARATOR
2 BIT COMPARATORLEVEL-2 BIT COMPARATOR
LEVEL-2 BIT COMPARATOREXPT-1 LOGIC GATES
EXPT-1 LOGIC GATESEXPT-1 LEVEL2
EXPT-1 LEVEL2