3 input full adder

4:1 DEMUX NAND

Experiment 1 : Logic Gates

2 input half subtractor(nand)

3 input full adder (nand)

2:1 MUX BASIC

4:1 MUX BASIC

1:2 DEMUX BASIC

1:4 DEMUX BASIC

4:1 MUX NAND

2:1 MUX NAND

exp 5 level 1 basic gates

EXPERIMENT 1 level 2

jk logic

1:2 DEMUX NAND

2:4 DECODER

4:2 binary encoder

4:2 PRIORITY ENCODER

2 input half adder

2 input half subtractor

3 input full subtractor

3 input full subtractor (nand)

FLIP FLOP

JK FLIP FLOP

D FLIP FLOP

T FLIP FLOP

jk 4 bit

2 input half adder(nand)

SR FLIP FLOP