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3 input full adder
3 input full adder4:1 DEMUX NAND
4:1 DEMUX NANDExperiment 1 : Logic Gates
Experiment 1 : Logic Gates2 input half subtractor(nand)
2 input half subtractor(nand)3 input full adder (nand)
3 input full adder (nand)2:1 MUX BASIC
2:1 MUX BASIC4:1 MUX BASIC
4:1 MUX BASIC1:2 DEMUX BASIC
1:2 DEMUX BASIC1:4 DEMUX BASIC
1:4 DEMUX BASIC4:1 MUX NAND
4:1 MUX NAND2:1 MUX NAND
2:1 MUX NANDexp 5 level 1 basic gates
exp 5 level 1 basic gatesjk logic
jk logic1:2 DEMUX NAND
1:2 DEMUX NAND2:4 DECODER
2:4 DECODER4:2 binary encoder
4:2 binary encoder4:2 PRIORITY ENCODER
4:2 PRIORITY ENCODER2 input half adder
2 input half adder2 input half subtractor
2 input half subtractor3 input full subtractor
3 input full subtractor3 input full subtractor (nand)
3 input full subtractor (nand)FLIP FLOP
FLIP FLOPJK FLIP FLOP
JK FLIP FLOPD FLIP FLOP
D FLIP FLOPT FLIP FLOP
T FLIP FLOPjk 4 bit
jk 4 bit2 input half adder(nand)
2 input half adder(nand)EXPERIMENT 1 level 2
EXPERIMENT 1 level 2SR FLIP FLOP
SR FLIP FLOP