project.name

Aditya VS

Member since: 1 year

Educational Institution: Not Entered

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3 input full adder

3 input full adder
Public
project.name

4:1 DEMUX NAND

4:1 DEMUX NAND
Public
project.name

Experiment 1 : Logic Gates

Experiment 1 : Logic Gates
Public
project.name

2 input half subtractor(nand)

2 input half subtractor(nand)
Public
project.name

3 input full adder (nand)

3 input full adder (nand)
Public
project.name

2:1 MUX BASIC

2:1 MUX BASIC
Public
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4:1 MUX BASIC

4:1 MUX BASIC
Public
project.name

1:2 DEMUX BASIC

1:2 DEMUX BASIC
Public
project.name

1:4 DEMUX BASIC

1:4 DEMUX BASIC
Public
project.name

4:1 MUX NAND

4:1 MUX NAND
Public
project.name

2:1 MUX NAND

2:1 MUX NAND
Public
project.name

exp 5 level 1 basic gates

exp 5 level 1 basic gates
Public
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jk logic

jk logic
Public
project.name

1:2 DEMUX NAND

1:2 DEMUX NAND
Public
project.name

2:4 DECODER

2:4 DECODER
Public
project.name

4:2 binary encoder

4:2 binary encoder
Public
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4:2 PRIORITY ENCODER

4:2 PRIORITY ENCODER
Public
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2 input half adder

2 input half adder
Public
project.name

2 input half subtractor

2 input half subtractor
Public
project.name

3 input full subtractor

3 input full subtractor
Public
project.name

3 input full subtractor (nand)

3 input full subtractor (nand)
Public
project.name

FLIP FLOP

FLIP FLOP
Public
project.name

JK FLIP FLOP

JK FLIP FLOP
Public
project.name

D FLIP FLOP

D FLIP FLOP
Public
project.name

T FLIP FLOP

T FLIP FLOP
Public
project.name

jk 4 bit

jk 4 bit
Public
project.name

2 input half adder(nand)

2 input half adder(nand)
Public
project.name

EXPERIMENT 1 level 2

EXPERIMENT 1 level 2
Public
project.name

SR FLIP FLOP

SR FLIP FLOP
Public
project.name
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