project.name

the wolf

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demultiplexor 1 a 4 modulado

demultiplexor 1 a 4 modulado
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Resistro 1 palabra

Resistro 1 palabra
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CPU ALU

CPU ALU
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maxterminos1

maxterminos1
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Restador

Restador
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Alu restador

Alu restador
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parcial1

parcial1
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Unidad Aritmetica

Unidad Aritmetica
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1 A 4 DEMULTIPLEXOR

1 A 4 DEMULTIPLEXOR
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primer ejercicio con ors xdxd

primer ejercicio con ors xdxd
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flip-flops

flip-flops
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Untitled

Untitled
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xdxdxdxd

xdxdxdxd
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Contador Ascendente y Descendete

Contador Ascendente y Descendete
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Untitled

Untitled
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Demultiplexor 1 a 2

Demultiplexor 1 a 2
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SUMA/RESTA

SUMA/RESTA
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Asynchronous Counter

Asynchronous Counter
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UAL

UAL
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memoria

memoria
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CPU

CPU
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Splitter

Splitter
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biestable maestro-esclavo

biestable maestro-esclavo
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multiplexor 4 a 1 origen

multiplexor 4 a 1 origen
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Sumador Completo

Sumador Completo
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RARO

RARO
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Unidad Logica

Unidad Logica
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Untitled

Untitled
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multiplexor 2/1 simplificado

multiplexor 2/1 simplificado
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primer wa

primer wa
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primer wa

primer wa
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ejercicio 1

ejercicio 1
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ejercicio numero1

ejercicio numero1
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primer ejercicio con ors xdxd

primer ejercicio con ors xdxd
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mintermino1

mintermino1
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multiplexor minitermino

multiplexor minitermino
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multiplexador 4 a 1 xd

multiplexador 4 a 1 xd
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mutiplexor 8 a 1 origen

mutiplexor 8 a 1 origen
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multiplexor 8a 1 modulado

multiplexor 8a 1 modulado
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demultiplexor 2a1 min y max

demultiplexor 2a1 min y max
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demultiplexor 1 a 4

demultiplexor 1 a 4
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DEMULTIPLEXOR 1 a 4 modular version 2

DEMULTIPLEXOR 1 a 4 modular version 2
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Seven-Segment_Display

Seven-Segment_Display
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segmente compuertas

segmente compuertas
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DEMULTIPLEXOR 1 A 8

DEMULTIPLEXOR 1 A 8
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demulti 1 a 8 version 2

demulti 1 a 8 version 2
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Sumador 2 numeros

Sumador 2 numeros
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unidad aritmetica

unidad aritmetica
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unidad logica

unidad logica
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xdsa

xdsa
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latches

latches
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latches sr reloj

latches sr reloj
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flip-flip D

flip-flip D
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biestable jk maestro esclavo

biestable jk maestro esclavo
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Biestable JK activado por flancos

Biestable JK activado por flancos
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biestable D con retardo

biestable D con retardo
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Latch D

Latch D
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Biestable Rs utilizando No-y

Biestable Rs utilizando No-y
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memoria

memoria
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Parcial, contador programable

Parcial, contador programable
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parcial2 conta-registro

parcial2 conta-registro
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Alu

Alu
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Version 2 Alu-Registro

Version 2 Alu-Registro
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ALu 2 bits

ALu 2 bits
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CPU Ram-Rom

CPU Ram-Rom
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Cpu con Contadores

Cpu con Contadores
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Untitled

Untitled
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final

final
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OTRO MAS

OTRO MAS
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DEMULTIPLEXOR 1 A 8 MODULADO

DEMULTIPLEXOR 1 A 8 MODULADO
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parcial Alu

parcial Alu
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Actividad_TercerCorte Alu-Registro

Actividad_TercerCorte Alu-Registro
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contadores

contadores
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parcial version 2

parcial version 2
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CPU

CPU
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decodificador segmente ands

decodificador segmente ands
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latches d con reloj

latches d con reloj
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Decodificador binário-decimal (Display de 7 segmentos)

Decodificador binário-decimal (Display de 7 segmentos)
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Seven-Segment_Display

Seven-Segment_Display
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Unidad Logica

Unidad Logica
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Unidad Aritmetica

Unidad Aritmetica
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SUMA/RESTA

SUMA/RESTA
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UAL

UAL
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Splitter

Splitter
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