project.name

darwin zambrano

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

taller 1

taller 1
Public
project.name

taller 2

taller 2
Public
project.name

Untitled

Untitled
Public
project.name

4 A 1

4 A 1
Public
project.name

2 A 1

2 A 1
Public
project.name

8 A 1 AND Y OR

8 A 1 AND Y OR
Public
project.name

8 A 1 MULTIPLEXORES

8 A 1 MULTIPLEXORES
Public
project.name

4 A 1 MULTIPLEXORES

4 A 1 MULTIPLEXORES
Public
project.name

2 A 1 SIMPLIFICADO

2 A 1 SIMPLIFICADO
Public
project.name

2A 1 MULTIPLEXORES

2A 1 MULTIPLEXORES
Public
project.name

2 A 1 DEMULTIPLEXOR

2 A 1 DEMULTIPLEXOR
Public
project.name

2A1 AND

2A1 AND
Public
project.name

2 A 1 OR

2 A 1 OR
Public
project.name

1 A 4 DEMULTIPLEXOR

1 A 4 DEMULTIPLEXOR
Public
project.name

1 A 4 DEMULTIPLEXOR

1 A 4 DEMULTIPLEXOR
Public
project.name

SUMATORIA

SUMATORIA
Public
project.name

SUMADOR COMPLETO

SUMADOR COMPLETO
Public
project.name

SUMA/RESTA

SUMA/RESTA
Public
project.name

latches SR

latches SR
Public
project.name

Biestable latches SR con reloj

Biestable latches SR con reloj
Public
project.name

Flip Flop D

Flip Flop D
Public
project.name

Biestable SR maestro-esclavo.

Biestable SR maestro-esclavo.
Public
project.name

Biestable tipo JK.

Biestable tipo JK.
Public
project.name

Registro de tres bits

Registro de tres bits
Public
project.name

Contador de 4 bits

Contador de 4 bits
Public
project.name

Memoria

Memoria
Public
project.name

PARCIAL 2

PARCIAL 2
Public
project.name

cpu alu entrada y salida

cpu alu entrada y salida
Public
project.name

Cpu con unidad aritmético lógica, registros y memorias de datos y de programa

Cpu con unidad aritmético lógica, registros y memorias de datos y de programa
Public
project.name

Biestable SR sincrónico con entradas asincrónicas

Biestable SR sincrónico con entradas asincrónicas
Public
project.name

Biestable latches D con reloj

Biestable latches D con reloj
Public
project.name

Unidad aritmetica logica

Unidad aritmetica logica
Public
project.name

Unidad logica

Unidad logica
Public
project.name

RESTADOR COMPLETO

RESTADOR COMPLETO
Public
project.name

DEMULTIPLEXOR 8 A 1 MUDULAR

DEMULTIPLEXOR 8 A 1 MUDULAR
Public
project.name

Seven-Segment_Display

Seven-Segment_Display
Public
project.name
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darwin zambrano is not a collaborator of any project.