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darwin zambrano

Member since: 4 years

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taller 1

taller 1
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taller 2

taller 2
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Untitled

Untitled
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4 A 1

4 A 1
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2 A 1

2 A 1
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8 A 1 AND Y OR

8 A 1 AND Y OR
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8 A 1 MULTIPLEXORES

8 A 1 MULTIPLEXORES
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4 A 1 MULTIPLEXORES

4 A 1 MULTIPLEXORES
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2 A 1 SIMPLIFICADO

2 A 1 SIMPLIFICADO
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2A 1 MULTIPLEXORES

2A 1 MULTIPLEXORES
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2 A 1 DEMULTIPLEXOR

2 A 1 DEMULTIPLEXOR
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2A1 AND

2A1 AND
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2 A 1 OR

2 A 1 OR
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1 A 4 DEMULTIPLEXOR

1 A 4 DEMULTIPLEXOR
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1 A 4 DEMULTIPLEXOR

1 A 4 DEMULTIPLEXOR
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DEMULTIPLEXOR 8 A 1 MUDULAR

DEMULTIPLEXOR 8 A 1 MUDULAR
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SUMATORIA

SUMATORIA
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SUMADOR COMPLETO

SUMADOR COMPLETO
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SUMA/RESTA

SUMA/RESTA
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latches SR

latches SR
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Biestable latches SR con reloj

Biestable latches SR con reloj
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Flip Flop D

Flip Flop D
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Biestable SR maestro-esclavo.

Biestable SR maestro-esclavo.
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Biestable tipo JK.

Biestable tipo JK.
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Registro de tres bits

Registro de tres bits
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Contador de 4 bits

Contador de 4 bits
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Memoria

Memoria
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PARCIAL 2

PARCIAL 2
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cpu alu entrada y salida

cpu alu entrada y salida
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Cpu con unidad aritmético lógica, registros y memorias de datos y de programa

Cpu con unidad aritmético lógica, registros y memorias de datos y de programa
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Biestable SR sincrónico con entradas asincrónicas

Biestable SR sincrónico con entradas asincrónicas
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Biestable latches D con reloj

Biestable latches D con reloj
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Unidad aritmetica logica

Unidad aritmetica logica
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Unidad logica

Unidad logica
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RESTADOR COMPLETO

RESTADOR COMPLETO
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Seven-Segment_Display

Seven-Segment_Display
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