De Morgan's Law is demonstrated by showing here that this memory circuit can be built from two NAND gates or NOR gates.Set state: store a 1

• Set state: store a 1
• Reset state: store a 0

The resting state of the NAND composed SR latch, meaning it retains its current output in the hypothetical memory, is when the inputs: 1 1 are on. This is because the set and reset are active-low inputs. When one of the inputs are 0, the state of the machine changes.

Therefore, for this circuit 0 0 is an invalid input, not allowed. The output would be 1 1 which would be like saying set and don't set the memory state. The memory state can only be one thing at a time: 0 or 1.

The NOR gate composed circuit is active-high, so the invalid inputs is 1 1. The output would be  0 0 which is like saying the memory state is off but it also isn't off.