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Incubated From:
Author: OTAVIO AUGUSTO GUIMARAES FERREIRA
Forked from: Karthik Kingster/Lab 5
Project access type: Public
Description:
ENG103Digital Electronics DesignLab Experiment 5 (Online Simulator)Designing Sequential Circuit Using D FFName of the Candidate:Student PI No. : LAB Experiment 5 – Designing Sequential Circuit Using D Flip-flops____________________________________________________________________________
ENG103 Lab Expt 5 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 2 of 5OBJECTIVES: To appreciate the concepts of State diagram and State table.To design sequential circuit using D flip-flops and combinational logic circuits.To use DeMorgan’s Theorem to construct the combinational logic part of the circuit using only NAND gates.To wire up the sequential circuit using online simulator CircuitVerse. (https://circuitverse.org/)In this part of the experiment, you will determine the behaviour of the sequential circuit shown in Figure 5a. 1.First, you must derive the Boolean functions of the state-decoding logics. Using DeMorgan’s Theorem, redesign the combinational logic part of the circuit, to replace ENG103 Lab Expt 5 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 3 of 5the AND gates and OR gates with NAND gates only. Show your new Boolean expressions. Derived Booleans: New NAND only Booleans:ENG103 Lab Expt 5 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 4 of 52.Implement the circuit with D flip-flops and NAND gates only using the online simulator. Probe the clock, QA, QB, and QC timing signals. Screen captures the circuit and show it below.3.Observe the various states of the circuit and record all possible states of the circuits in Table E5. You may need to apply a slower clock signal. To get to the unused state, you will need to disable the clock and preset the filp-flops to the unused states first before reapplying the clock pulse. The clock could be enabled or disabled in the project properties. Async RESET and PRESET are used to preset the flip-flops.Table E5Current StateQAQBQCNext StateQAQBQC000001001010010011011100100101101000110000111000ENG103 Lab Expt 5 SINGAPORE UNIVERISTY OF SOCIAL SCIENCES (SUSS) Page 5 of 54.Screen captures the timing diagram for the clock, QA, QB, and QC below, showing all the possible transition states.5.Switch off the clock by disabling it in the project properties of the simulator. Observe what happens and record the state of the circuit.The circuit state stopped changing when the clock pulse is disabled. As such, any value from 0 to 5 inclusive recorded should be acceptable.6.Switch on the clock by enabling it in the project properties of the simulator. Observe and describe what happens.When the clock pulse is reapplied, the circuit start counting normally again.7.Draw a state diagram for this circuit and state the function of the circuit
Created: Mar 14, 2023
Updated: Aug 27, 2023
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