Shani soni
Member since: 1 year
Educational Institution: Ajay Kumar Garg Engineering College, Gaziabad
Country: India
4X1 MULTIPLEXER
4X1 MULTIPLEXER
Public
Manish chauhan
Manish chauhan
Public
3:8 Line decoder
3:8 Line decoder
Public
FULL ADDER
FULL ADDER
Public
3 to 8 line decoder
3 to 8 line decoder
Public
Verify the excitation tables of various FLIP-FLOPS.
Verify the excitation tables of various FLIP-FLOPS.
Public
Design the data path of a computer from its register transfer language description.
Design the data path of a computer from its register transfer language description.
Public
Control Unit
Control Unit
Public
half adder
half adder
Public
4-Bit Synchronous Decade Counter
4-Bit Synchronous Decade Counter
Public
FULL ADDER USING BASIC LOGIC GATES
FULL ADDER USING BASIC LOGIC GATES
Public
Design of an 8-bit Input/ Output system with 4-bit Internal Registers
Design of an 8-bit Input/ Output system with 4-bit Internal Registers
Public
4 BIT CLA
4 BIT CLA
Public
Shani Soni
Shani Soni
Public
8X1 MULTIPLEXER
8X1 MULTIPLEXER
Public
8 BIT ALU
8 BIT ALU
Public
SIMPLE COMPUTER
SIMPLE COMPUTER
Public
Binary -to -Gray, Gray -to -Binary code converte
Binary -to -Gray, Gray -to -Binary code converte
Public
4X1 MULTIPLEXER
4X1 MULTIPLEXER
Public
8X1 MULTIPLEXER
8X1 MULTIPLEXER
Public
Design of an 8-bit Input/ Output system with 4-bit Internal Registers
Design of an 8-bit Input/ Output system with 4-bit Internal Registers
Public
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