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Tito Tom

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

CPU

CPU
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Traffic_light1

Traffic_light1
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TP2

TP2
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TP2

TP2
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TP2

TP2
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4:2 Encoder

4:2 Encoder
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TP3

TP3
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Memory 8 bits data input on 6 bits or 64 address

Memory 8 bits data input on 6 bits or 64 address
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Project 2

Project 2
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Modulo 10 and 16

Modulo 10 and 16
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CPU

CPU
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TP5

TP5
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RAM

RAM
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count 0 to 10

count 0 to 10
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TP2

TP2
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down counter 10

down counter 10
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Assignment

Assignment
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D counter 0-5

D counter 0-5
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Divisor_binary

Divisor_binary
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Project 1

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