RS Flip Flop
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Author: Guitterez, R

Project access type: Public

Description:

Clock Input Inputs Outputs Comments J K Q Q’ 0 X X Same as previous Same as previous No change 1 0 0 Same as previous Same as previous No change 1 0 1 0 1 Reset 1 1 0 1 0 Set 1 1 1 Opposite of previous Opposite of previous Toggle




Here, Q is the present state and Q’ is the next state. As you can see, when J, K and Clock are equal to 1, toggling takes place, i.e. The next state will be equal to the complement of the present state.

Now, let us look at the timing diagram of JK flip-flop.

As you already know, when J, K and Clock are equal to 1, toggling takes place. Here, propagation delay has also been reduced, so the output will be given out at the instant input is given. So there is a toggling again. Therefore, whenever Clock is equal to 1 there are consecutive toggling. This condition is called as Race around condition. To put it in words, “ For JK flip-flop if J, K and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition. “’ This condition also exists in T flip-flop since T flip-flop also has toggling options.

Created: Nov 16, 2022

Updated: Aug 27, 2023


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