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Aashish Maharjan

Member since: 1 year

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VerificationQ1

VerificationQ1
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Spring 2017 Sec B

Spring 2017 Sec B
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VerificationofBooleanLaws1

VerificationofBooleanLaws1
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VerifyQ1a

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VerifyQ2a

VerifyQ2a
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Lab 7: Adders / Subtractors

Lab 7: Adders / Subtractors
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Practice Circuits

Practice Circuits
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NAND GATE

NAND GATE
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Inverter

Inverter
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AND GATE

AND GATE
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Distributive

Distributive
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7 segment decoder

7 segment decoder
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VerifyQ2b

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VerifyQ5

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Multiplexer and Dupliplexer

Multiplexer and Dupliplexer
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XOR using NOR

XOR using NOR
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Sequence Detector

Sequence Detector
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Latches and Flip-flops

Latches and Flip-flops
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Lab 16: Design 3 bit synchronous up/down counter

Lab 16: Design 3 bit synchronous up/down counter
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4 bit ripple counter

4 bit ripple counter
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OR GATE

OR GATE
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Universal Shift Register

Universal Shift Register
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Combinational Logic

Combinational Logic
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X+X'=1

X+X'=1
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Untitled

Untitled
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VerifyQ1b

VerifyQ1b
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NOR GATE

NOR GATE
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VerifyQ4

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