project.name

ZhiMeng Cheng

Member since: 2 years

Educational Institution: Not Entered

Country: Malaysia

D2_Circuit_3_1_ZHIMENG

D2_Circuit_3_1_ZHIMENG
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Circuit_2

Circuit_2
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Shift Registers

Shift Registers
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Divide-3 counter

Divide-3 counter
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Untitled

Untitled
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Shift_Register

Shift_Register
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D2_Circuit_3_1

D2_Circuit_3_1
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Untitled

Untitled
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4-to-1 Multiplexer

4-to-1 Multiplexer
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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D Latch +ve level

D Latch +ve level
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Level Triggered SR Latch

Level Triggered SR Latch
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T3 (2.3)

T3 (2.3)
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ZM'S DESIGN

ZM'S DESIGN
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Divide 3 counter

Divide 3 counter
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3 to 8 decoder

3 to 8 decoder
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Full adder

Full adder
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Ripple Counter (Asynchronous)

Ripple Counter (Asynchronous)
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Registers

Registers
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tristate buffer

tristate buffer
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Bidirectional Shift Registers

Bidirectional Shift Registers
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SR Latch Active Low

SR Latch Active Low
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D Flip-flop

D Flip-flop
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D-Flip Flop (Master-Slave)

D-Flip Flop (Master-Slave)
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Sequence_Detector

Sequence_Detector
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Divide-by-4 rippler counter (Synchronous)

Divide-by-4 rippler counter (Synchronous)
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Carry Bypass Adder

Carry Bypass Adder
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16bits_Carry_Bypass_Adder

16bits_Carry_Bypass_Adder
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Sequence_Detector

Sequence_Detector
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Untitled

Untitled
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D2_Circuit_3_1

D2_Circuit_3_1
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D2_Circuit_3_1_ZHIMENG

D2_Circuit_3_1_ZHIMENG
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Shift_Register

Shift_Register
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Untitled

Untitled
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