You must login before you can post a comment.
Incubated From:
Author: Roddy Khelawan
Forked from: Roddy Khelawan/D Latch
Project access type: Public
Description:
D Flip Flop (Negative Edge Triggered)
Q follows D whenever /CLK transitions from High to Low.
Q remains unchanged in all other cases.
Consider /CLK as a ticking clock (square wave).
What we have is a 1 bit register. The state of Q is held until a clock transition, negative in this case, causes Q to 'read' Ds state.
Created: Feb 12, 2021
Updated: Aug 26, 2023
Comments