Trinity Caskey
Member since: 2 years
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1.3.3
1.3.3
Public
1.3.3 Pt.2
1.3.3 Pt.2
Public
Untitled
Untitled
Public
1.3.3
1.3.3
Public
4/27
4/27
Public
1.3.2 Sequential Logic
1.3.2 Sequential Logic
Public
Fireplace pt. 2
Fireplace pt. 2
Public
2.1 Majority Vote Project Pt2
2.1 Majority Vote Project Pt2
Public
Final Circuit
Final Circuit
Public
Date of Birth progect
Date of Birth progect
Public
2.1 Majority Vote Project Pt. 3
2.1 Majority Vote Project Pt. 3
Public
Design Process Exam Pt:2
Design Process Exam Pt:2
Public
Semester 1 Exam pt. 3
Semester 1 Exam pt. 3
Public
0-19 Counter
0-19 Counter
Public
Seven Segment Display
Seven Segment Display
Public
NAND
NAND
Public
3-Bit Binary-Down Counter
3-Bit Binary-Down Counter
Public
Semester 2 exam Part 1: Performance Document A
Semester 2 exam Part 1: Performance Document A
Public
3.2.1 Asynchronous counter
3.2.1 Asynchronous counter
Public
3.3.1 Synchronous Counter
3.3.1 Synchronous Counter
Public
0-5 Synchronous Up Counter
0-5 Synchronous Up Counter
Public
D Flip-Flop
D Flip-Flop
Public
J/K Flip-Flop
J/K Flip-Flop
Public
3.1.2 Flip-Flop Applications
3.1.2 Flip-Flop Applications
Public
0-7 Synchronous Down Counter
0-7 Synchronous Down Counter
Public
3.2.2 Asynchronous Modulus Counters
3.2.2 Asynchronous Modulus Counters
Public
334 Now Serving Display
334 Now Serving Display
Public
NOR
NOR
Public
3.3.2 MSI Synchronous Counter (74LS163)
3.3.2 MSI Synchronous Counter (74LS163)
Public
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