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Rahul Patil

Member since: 1 year

Educational Institution: Not Entered

Country: Not Entered

circuit3task3

circuit3task3
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task3 mux

task3 mux
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task3circuit3

task3circuit3
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Circuit5task3

Circuit5task3
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Circuit6ask3

Circuit6ask3
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3*8 DECODER USING TWO 2*4 DECODERS

3*8 DECODER USING TWO 2*4 DECODERS
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1x4 Demux using 2 to 4 Decoder

1x4 Demux using 2 to 4 Decoder
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SOP 2:1 MUX design using AOI logic

SOP 2:1 MUX design using AOI logic
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SOP 2:1 MUX design using AOI logic

SOP 2:1 MUX design using AOI logic
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circuit11task3

circuit11task3
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two complement multiplexer

two complement multiplexer
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Untitled

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Untitled

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Q2

Q2
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Untitled

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Untitled

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Circuit4task3

Circuit4task3
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Circuit7Task3

Circuit7Task3
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2*4 Decoder

2*4 Decoder
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circuit12task3

circuit12task3
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Untitled

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Task4

Task4
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4 BIT ALU

4 BIT ALU
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DA1q8

DA1q8
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Untitled

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circuit8Task3

circuit8Task3
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2 to 4 Line Decoder

2 to 4 Line Decoder
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