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circuit3task3
circuit3task3task3 mux
task3 muxtask3circuit3
task3circuit3Circuit5task3
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Circuit6ask33*8 DECODER USING TWO 2*4 DECODERS
3*8 DECODER USING TWO 2*4 DECODERS1x4 Demux using 2 to 4 Decoder
1x4 Demux using 2 to 4 DecoderSOP 2:1 MUX design using AOI logic
SOP 2:1 MUX design using AOI logiccircuit11task3
circuit11task3two complement multiplexer
two complement multiplexerUntitled
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Q2Untitled
UntitledUntitled
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Circuit4task3Circuit7Task3
Circuit7Task32*4 Decoder
2*4 Decodercircuit12task3
circuit12task3Untitled
UntitledTask4
Task4DA1q8
DA1q8Untitled
Untitledcircuit8Task3
circuit8Task3SOP 2:1 MUX design using AOI logic
SOP 2:1 MUX design using AOI logic2 to 4 Line Decoder
2 to 4 Line Decoder4 BIT ALU
4 BIT ALU