project.name

Ranjit

Member since: 2 years

Educational Institution: presidency university banglore

Country: India

demux

demux
Public
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8:1 mux using 4:1

8:1 mux using 4:1
Public
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func

func
Public
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Untitled

Untitled
Public
project.name

logic gate 1 7/10

logic gate 1 7/10
Public
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Untitled

Untitled
Public
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all gates

all gates
Public
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all gates

all gates
Public
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half adder full adder

half adder full adder
Public
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half adder full adder

half adder full adder
Public
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mux

mux
Public
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full adder using hal;f

full adder using hal;f
Public
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Untitled

Untitled
Public
project.name
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