JAGANNATH VUNGARALA
Member since: 2 years
Educational Institution: presidency university
Country: India
ENCODER
ENCODER
Public
DECODERS
DECODERS
Public
m(0,1,3,6,7) using 4:1 mux & 8:1 mux
m(0,1,3,6,7) using 4:1 mux & 8:1 mux
Public
8:1 mux using 4:1 and 2:1
8:1 mux using 4:1 and 2:1
Public
1st project
1st project
Public
experiment 1 (f1)
experiment 1 (f1)
Public
deriving xor gate nand gates
deriving xor gate nand gates
Public
Deriving XNOR gate using NAND gate
Deriving XNOR gate using NAND gate
Public
d flip flop
d flip flop
Public
experiment 1 (f2)
experiment 1 (f2)
Public
sr flip flops
sr flip flops
Public
implementing full adder using half adder
implementing full adder using half adder
Public
implementing full adder using baic gates
implementing full adder using baic gates
Public
ha and fa
ha and fa
Public
MUX
MUX
Public
all basic gates
all basic gates
Public
DEMUX
DEMUX
Public
8:1 mux using 4:1 and 2:1
8:1 mux using 4:1 and 2:1
Public
m(0,1,3,6,7) using 4:1 mux & 8:1 mux
m(0,1,3,6,7) using 4:1 mux & 8:1 mux
Public
half adder and full adder using 4:1 & 2:1
half adder and full adder using 4:1 & 2:1
Public
Deriving XOR gate using NOR gate
Deriving XOR gate using NOR gate
Public
16:1 using 8:1,4:1,2:1 mux
16:1 using 8:1,4:1,2:1 mux
Public
Deriving XNOR gate using NOR gate
Deriving XNOR gate using NOR gate
Public
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