project.name

VARSHITH GAJJALA

Member since: 2 years

Educational Institution: Not Entered

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ENCODER BLOCK 2;1,4;2,8;3

ENCODER BLOCK 2;1,4;2,8;3
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4:1 MUX

4:1 MUX
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2:1 8:1

2:1 8:1
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EXPERIMENT OF LOGIC GATES

EXPERIMENT OF LOGIC GATES
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circuit11

circuit11
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PROJECT 2

PROJECT 2
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half adder and full adder using 4:1 & 2:1

half adder and full adder using 4:1 & 2:1
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half adder and full adder using 4:1 & 2:1

half adder and full adder using 4:1 & 2:1
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implementing half adder

implementing half adder
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Untitled

Untitled
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Untitled

Untitled
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4x1 Multiplexer

4x1 Multiplexer
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HALF ADDER

HALF ADDER
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HALF ADDAR AND FULL ADDAR USING 4:1 & 2:1

HALF ADDAR AND FULL ADDAR USING 4:1 & 2:1
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project 3

project 3
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ENCODER BLOCK 2;1,4;2,8;3

ENCODER BLOCK 2;1,4;2,8;3
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m(0,1,3,6,7) using 4:1 mux & 8:1 mux

m(0,1,3,6,7) using 4:1 mux & 8:1 mux
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16:1 using 8:1,4:1,2:1 mux

16:1 using 8:1,4:1,2:1 mux
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8:1 mux using 4:1 and 2:1

8:1 mux using 4:1 and 2:1
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