Abhishek Kumar Rai
Member since: 2 years
Educational Institution: Not Entered
Country: Not Entered
Latches Flip Flop
Latches Flip Flop
Gi
Gi
4x1 mux
4x1 mux
4x1 mux
4x1 mux
4*1 Multiplexer
4*1 Multiplexer
4-bit shift register with parellel load compression (lab 12)
4-bit shift register with parellel load compression (lab 12)
4 Bit Paraller Adder and Subtractor
4 Bit Paraller Adder and Subtractor
4-Bit Parallel Adder-Subtractor
4-Bit Parallel Adder-Subtractor
Untitled
Untitled
Half Adder
Half Adder
Gray To Binary
Gray To Binary
Binary To Gray
Binary To Gray
4 - Bit Arithmetic Unit
4 - Bit Arithmetic Unit
DECODER
DECODER
Untitled
Untitled
arithmetic
arithmetic
4 Bit Adder
4 Bit Adder
SR Flip Flop
SR Flip Flop
D Flip Flop
D Flip Flop
JK Fip Flop
JK Fip Flop
Untitled
Untitled
Flip Flop
Flip Flop
JK Master Slave FlipFlop
JK Master Slave FlipFlop
(Master Slave JK Flip Flop)
(Master Slave JK Flip Flop)
Datapath
Datapath
4-bit shift register with parellel load compression (lab 12)
4-bit shift register with parellel load compression (lab 12)
4 BIT ALU
4 BIT ALU
Design the data path of a computer from its register transfer language description
Design the data path of a computer from its register transfer language description
Design the data path of a computer from its register transfer language description
Design the data path of a computer from its register transfer language description
Temp
Temp
Design the data path of a computer from its register transfer language description
Design the data path of a computer from its register transfer language description
4x1 Multiplexer
4x1 Multiplexer
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